drm/amdgpu/vcn:Add DPG mode Register XX check (368d0dd8) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

+8 −0

Original line number	Diff line number	Diff line
		@@ -37,6 +37,11 @@

		#include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"

		#define mmUVD_RBC_XX_IB_REG_CHECK 0x05ab
		#define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1
		#define mmUVD_REG_XX_MASK 0x05ac
		#define mmUVD_REG_XX_MASK_BASE_IDX 1

		static int vcn_v1_0_stop(struct amdgpu_device *adev);
		static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
		static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
		@@ -1031,6 +1036,9 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)

		vcn_v1_0_mc_resume_dpg_mode(adev);

		WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
		WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);

		/* take all subblocks out of reset, except VCPU */
		WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET,
		UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 0xFFFFFFFF, 0);