Unverified Commit 367e5927 authored by Manivannan Sadhasivam's avatar Manivannan Sadhasivam
Browse files

arm64: dts: bitmain: Add GPIO support for BM1880 SoC 



Add GPIO support for Bitmain BM1880 SoC based on Designware APB GPIO
controller IP. IP exposes 3 GPIO controllers with a total of 72 pins.

Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 79a3aaa7

arch/arm64/boot/dts/bitmain/bm1880.dtsi

+54 −0
Original line number Diff line number Diff line
@@ -80,6 +80,60 @@ 
			#interrupt-cells = <3>;

		};



		gpio0: gpio@50027000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";

			reg = <0x0 0x50027000 0x0 0x400>;



			porta: gpio-controller@0 {

				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				#gpio-cells = <2>;

				snps,nr-gpios = <32>;

				reg = <0>;

				interrupt-controller;

				#interrupt-cells = <2>;

				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;

			};

		};



		gpio1: gpio@50027400 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";

			reg = <0x0 0x50027400 0x0 0x400>;



			portb: gpio-controller@0 {

				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				#gpio-cells = <2>;

				snps,nr-gpios = <32>;

				reg = <0>;

				interrupt-controller;

				#interrupt-cells = <2>;

				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;

			};

		};



		gpio2: gpio@50027800 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";

			reg = <0x0 0x50027800 0x0 0x400>;



			portc: gpio-controller@0 {

				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				#gpio-cells = <2>;

				snps,nr-gpios = <8>;

				reg = <0>;

				interrupt-controller;

				#interrupt-cells = <2>;

				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;

			};

		};



		uart0: serial@58018000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x0 0x58018000 0x0 0x2000>;

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