Commit 367069f1 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'next/dt' of git://git.linaro.org/people/arnd/arm-soc 

* 'next/dt' of git://git.linaro.org/people/arnd/arm-soc:
  ARM: gic: use module.h instead of export.h
  ARM: gic: fix irq_alloc_descs handling for sparse irq
  ARM: gic: add OF based initialization
  ARM: gic: add irq_domain support
  irq: support domains with non-zero hwirq base
  of/irq: introduce of_irq_init
  ARM: at91: add at91sam9g20 and Calao USB A9G20 DT support
  ARM: at91: dt: at91sam9g45 family and board device tree files
  arm/mx5: add device tree support for imx51 babbage
  arm/mx5: add device tree support for imx53 boards
  ARM: msm: Add devicetree support for msm8660-surf
  msm_serial: Add devicetree support
  msm_serial: Use relative resources for iomem

Fix up conflicts in arch/arm/mach-at91/{at91sam9260.c,at91sam9g45.c}
parents 81a3c10c c72dbae9

Documentation/devicetree/bindings/arm/fsl.txt

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i.MX51 Babbage Board

Required root node properties:

    - compatible = "fsl,imx51-babbage", "fsl,imx51";



i.MX53 Automotive Reference Design Board

Required root node properties:

    - compatible = "fsl,imx53-ard", "fsl,imx53";



i.MX53 Evaluation Kit

Required root node properties:

    - compatible = "fsl,imx53-evk", "fsl,imx53";



i.MX53 Quick Start Board

Required root node properties:

    - compatible = "fsl,imx53-qsb", "fsl,imx53";



i.MX53 Smart Mobile Reference Design Board

Required root node properties:

    - compatible = "fsl,imx53-smd", "fsl,imx53";

Documentation/devicetree/bindings/arm/gic.txt

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* ARM Generic Interrupt Controller



ARM SMP cores are often associated with a GIC, providing per processor

interrupts (PPI), shared processor interrupts (SPI) and software

generated interrupts (SGI).



Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.

Secondary GICs are cascaded into the upward interrupt controller and do not

have PPIs or SGIs.



Main node required properties:



- compatible : should be one of:

	"arm,cortex-a9-gic"

	"arm,arm11mp-gic"

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source.  The type shall be a <u32> and the value shall be 3.



  The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI

  interrupts.



  The 2nd cell contains the interrupt number for the interrupt type.

  SPI interrupts are in the range [0-987].  PPI interrupts are in the

  range [0-15].



  The 3rd cell is the flags, encoded as follows:

	bits[3:0] trigger type and level flags.

		1 = low-to-high edge triggered

		2 = high-to-low edge triggered

		4 = active high level-sensitive

		8 = active low level-sensitive

	bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of

	the 8 possible cpus attached to the GIC.  A bit set to '1' indicated

	the interrupt is wired to that CPU.  Only valid for PPI interrupts.



- reg : Specifies base physical address(s) and size of the GIC registers. The

  first region is the GIC distributor register base and size. The 2nd region is

  the GIC cpu interface register base and size.



Optional

- interrupts	: Interrupt source of the parent interrupt controller. Only

  present on secondary GICs.



Example:



	intc: interrupt-controller@fff11000 {

		compatible = "arm,cortex-a9-gic";

		#interrupt-cells = <3>;

		#address-cells = <1>;

		interrupt-controller;

		reg = <0xfff11000 0x1000>,

		      <0xfff10100 0x100>;

	};

Documentation/devicetree/bindings/tty/serial/msm_serial.txt

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* Qualcomm MSM UART



Required properties:

- compatible :

	- "qcom,msm-uart", and one of "qcom,msm-hsuart" or

	  "qcom,msm-lsuart".

- reg : offset and length of the register set for the device

	for the hsuart operating in compatible mode, there should be a

	second pair describing the gsbi registers.

- interrupts : should contain the uart interrupt.



There are two different UART blocks used in MSM devices,

"qcom,msm-hsuart" and "qcom,msm-lsuart".  The msm-serial driver is

able to handle both of these, and matches against the "qcom,msm-uart"

as the compatibility.



The registers for the "qcom,msm-hsuart" device need to specify both

register blocks, even for the common driver.



Example:



	uart@19c400000 {

		compatible = "qcom,msm-hsuart", "qcom,msm-uart";

		reg = <0x19c40000 0x1000>,

		      <0x19c00000 0x1000>;

		interrupts = <195>;

	};

arch/arm/boot/dts/at91sam9g20.dtsi

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/*

 * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC

 *

 *  Copyright (C) 2011 Atmel,

 *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>,

 *                2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

 *

 * Licensed under GPLv2 or later.

 */



/include/ "skeleton.dtsi"



/ {

	model = "Atmel AT91SAM9G20 family SoC";

	compatible = "atmel,at91sam9g20";

	interrupt-parent = <&aic>;



	aliases {

		serial0 = &dbgu;

		serial1 = &usart0;

		serial2 = &usart1;

		serial3 = &usart2;

		serial4 = &usart3;

		serial5 = &usart4;

		serial6 = &usart5;

	};

	cpus {

		cpu@0 {

			compatible = "arm,arm926ejs";

		};

	};



	memory@20000000 {

		reg = <0x20000000 0x08000000>;

	};



	ahb {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		apb {

			compatible = "simple-bus";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			aic: interrupt-controller@fffff000 {

				#interrupt-cells = <1>;

				compatible = "atmel,at91rm9200-aic";

				interrupt-controller;

				interrupt-parent;

				reg = <0xfffff000 0x200>;

			};



			dbgu: serial@fffff200 {

				compatible = "atmel,at91sam9260-usart";

				reg = <0xfffff200 0x200>;

				interrupts = <1>;

				status = "disabled";

			};



			usart0: serial@fffb0000 {

				compatible = "atmel,at91sam9260-usart";

				reg = <0xfffb0000 0x200>;

				interrupts = <6>;

				atmel,use-dma-rx;

				atmel,use-dma-tx;

				status = "disabled";

			};



			usart1: serial@fffb4000 {

				compatible = "atmel,at91sam9260-usart";

				reg = <0xfffb4000 0x200>;

				interrupts = <7>;

				atmel,use-dma-rx;

				atmel,use-dma-tx;

				status = "disabled";

			};



			usart2: serial@fffb8000 {

				compatible = "atmel,at91sam9260-usart";

				reg = <0xfffb8000 0x200>;

				interrupts = <8>;

				atmel,use-dma-rx;

				atmel,use-dma-tx;

				status = "disabled";

			};



			usart3: serial@fffd0000 {

				compatible = "atmel,at91sam9260-usart";

				reg = <0xfffd0000 0x200>;

				interrupts = <23>;

				atmel,use-dma-rx;

				atmel,use-dma-tx;

				status = "disabled";

			};



			usart4: serial@fffd4000 {

				compatible = "atmel,at91sam9260-usart";

				reg = <0xfffd4000 0x200>;

				interrupts = <24>;

				atmel,use-dma-rx;

				atmel,use-dma-tx;

				status = "disabled";

			};



			usart5: serial@fffd8000 {

				compatible = "atmel,at91sam9260-usart";

				reg = <0xfffd8000 0x200>;

				interrupts = <25>;

				atmel,use-dma-rx;

				atmel,use-dma-tx;

				status = "disabled";

			};

		};

	};

};

arch/arm/boot/dts/at91sam9g45.dtsi

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/*

 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC

 *                    applies to AT91SAM9G45, AT91SAM9M10,

 *                    AT91SAM9G46, AT91SAM9M11 SoC

 *

 *  Copyright (C) 2011 Atmel,

 *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>

 *

 * Licensed under GPLv2 or later.

 */



/include/ "skeleton.dtsi"



/ {

	model = "Atmel AT91SAM9G45 family SoC";

	compatible = "atmel,at91sam9g45";

	interrupt-parent = <&aic>;



	aliases {

		serial0 = &dbgu;

		serial1 = &usart0;

		serial2 = &usart1;

		serial3 = &usart2;

		serial4 = &usart3;

	};

	cpus {

		cpu@0 {

			compatible = "arm,arm926ejs";

		};

	};



	memory@70000000 {

		reg = <0x70000000 0x10000000>;

	};



	ahb {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		apb {

			compatible = "simple-bus";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			aic: interrupt-controller@fffff000 {

				#interrupt-cells = <1>;

				compatible = "atmel,at91rm9200-aic";

				interrupt-controller;

				interrupt-parent;

				reg = <0xfffff000 0x200>;

			};



			dma: dma-controller@ffffec00 {

				compatible = "atmel,at91sam9g45-dma";

				reg = <0xffffec00 0x200>;

				interrupts = <21>;

			};



			dbgu: serial@ffffee00 {

				compatible = "atmel,at91sam9260-usart";

				reg = <0xffffee00 0x200>;

				interrupts = <1>;

				status = "disabled";

			};



			usart0: serial@fff8c000 {

				compatible = "atmel,at91sam9260-usart";

				reg = <0xfff8c000 0x200>;

				interrupts = <7>;

				atmel,use-dma-rx;

				atmel,use-dma-tx;

				status = "disabled";

			};



			usart1: serial@fff90000 {

				compatible = "atmel,at91sam9260-usart";

				reg = <0xfff90000 0x200>;

				interrupts = <8>;

				atmel,use-dma-rx;

				atmel,use-dma-tx;

				status = "disabled";

			};



			usart2: serial@fff94000 {

				compatible = "atmel,at91sam9260-usart";

				reg = <0xfff94000 0x200>;

				interrupts = <9>;

				atmel,use-dma-rx;

				atmel,use-dma-tx;

				status = "disabled";

			};



			usart3: serial@fff98000 {

				compatible = "atmel,at91sam9260-usart";

				reg = <0xfff98000 0x200>;

				interrupts = <10>;

				atmel,use-dma-rx;

				atmel,use-dma-tx;

				status = "disabled";

			};

		};

	};

};

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