Commit 364e30eb authored by Larry Finger's avatar Larry Finger Committed by Greg Kroah-Hartman
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staging: r8723au: Add source files for new driver - part 4 



The Realtek USB device RTL8723AU is found in Lenovo Yoga 13 tablets.
A driver for it has been available in a GitHub repo for several months.
This commit contains the fourth part of source files. The source
is arbitrarily split to avoid E-mail files that are too large.

Jes Sorensen at RedHat has made many improvements to the vendor code,
and he has been doing the testing. I do not have access to this device.

Signed-off-by: default avatarLarry Finger <Larry.Finger@lwfinger.net>
Cc: Jes Sorensen <Jes.Sorensen@redhat.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent b1925ad8

drivers/staging/rtl8723au/include/Hal8723APhyCfg.h

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/******************************************************************************

 *

 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of version 2 of the GNU General Public License as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for

 * more details.

 *

 *

 ******************************************************************************/

#ifndef __INC_HAL8723PHYCFG_H__

#define __INC_HAL8723PHYCFG_H__



/*--------------------------Define Parameters-------------------------------*/

#define LOOP_LIMIT				5

#define MAX_STALL_TIME		50		/* us */

#define AntennaDiversityValue	0x80

#define MAX_TXPWR_IDX_NMODE_92S	63

#define Reset_Cnt_Limit		3





#define MAX_AGGR_NUM	0x0909



/*--------------------------Define Parameters-------------------------------*/





/*------------------------------Define structure----------------------------*/

enum swchnlcmdid {

	CmdID_End,

	CmdID_SetTxPowerLevel,

	CmdID_BBRegWrite10,

	CmdID_WritePortUlong,

	CmdID_WritePortUshort,

	CmdID_WritePortUchar,

	CmdID_RF_WriteReg,

};





/* 1. Switch channel related */

struct swchnlcmd {

	enum swchnlcmdid	CmdID;

	u32			Para1;

	u32			Para2;

	u32			msDelay;

};



enum HW90_BLOCK {

	HW90_BLOCK_MAC = 0,

	HW90_BLOCK_PHY0 = 1,

	HW90_BLOCK_PHY1 = 2,

	HW90_BLOCK_RF = 3,

	HW90_BLOCK_MAXIMUM = 4, /*  Never use this */

};



enum RF_RADIO_PATH {

	RF_PATH_A = 0,			/* Radio Path A */

	RF_PATH_B = 1,			/* Radio Path B */

	RF_PATH_C = 2,			/* Radio Path C */

	RF_PATH_D = 3,			/* Radio Path D */

	RF_PATH_MAX			/* Max RF number 90 support */

};



#define	RF_PATH_MAX			3



#define CHANNEL_MAX_NUMBER		14	/*  14 is the max channel number */

#define CHANNEL_GROUP_MAX		3	/*  ch1~3, ch4~9, ch10~14 total three groups */



enum WIRELESS_MODE {

	WIRELESS_MODE_UNKNOWN	= 0x00,

	WIRELESS_MODE_A		= BIT2,

	WIRELESS_MODE_B		= BIT0,

	WIRELESS_MODE_G		= BIT1,

	WIRELESS_MODE_AUTO	= BIT5,

	WIRELESS_MODE_N_24G	= BIT3,

	WIRELESS_MODE_N_5G	= BIT4,

	WIRELESS_MODE_AC	= BIT6

};



enum baseband_config_type {

	BaseBand_Config_PHY_REG = 0,			/* Radio Path A */

	BaseBand_Config_AGC_TAB = 1,			/* Radio Path B */

};



enum ra_offset_area {

	RA_OFFSET_LEGACY_OFDM1,

	RA_OFFSET_LEGACY_OFDM2,

	RA_OFFSET_HT_OFDM1,

	RA_OFFSET_HT_OFDM2,

	RA_OFFSET_HT_OFDM3,

	RA_OFFSET_HT_OFDM4,

	RA_OFFSET_HT_CCK,

};





/* BB/RF related */

enum rf_type_8190p {

	RF_TYPE_MIN,		/*  0 */

	RF_8225 = 1,		/*  1 11b/g RF for verification only */

	RF_8256 = 2,		/*  2 11b/g/n */

	RF_8258 = 3,		/*  3 11a/b/g/n RF */

	RF_6052 = 4,		/*  4 11b/g/n RF */

	RF_PSEUDO_11N = 5,	/*  5, It is a temporality RF. */

};



struct bb_reg_define {

	u32 rfintfs;		/*  set software control: */

				/*		0x870~0x877[8 bytes] */

	u32 rfintfi;		/*  readback data: */

				/*		0x8e0~0x8e7[8 bytes] */

	u32 rfintfo;		/*  output data: */

				/*		0x860~0x86f [16 bytes] */

	u32 rfintfe;		/*  output enable: */

				/*		0x860~0x86f [16 bytes] */

	u32 rf3wireOffset;	/*  LSSI data: */

				/*		0x840~0x84f [16 bytes] */

	u32 rfLSSI_Select;	/*  BB Band Select: */

				/*		0x878~0x87f [8 bytes] */

	u32 rfTxGainStage;	/*  Tx gain stage: */

				/*		0x80c~0x80f [4 bytes] */

	u32 rfHSSIPara1;	/*  wire parameter control1 : */

				/*		0x820~0x823, 0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] */

	u32 rfHSSIPara2;	/*  wire parameter control2 : */

				/*		0x824~0x827, 0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] */

	u32 rfSwitchControl; /* Tx Rx antenna control : */

				/*		0x858~0x85f [16 bytes] */

	u32 rfAGCControl1;	/* AGC parameter control1 : */

				/*	0xc50~0xc53, 0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] */

	u32 rfAGCControl2;	/* AGC parameter control2 : */

				/*		0xc54~0xc57, 0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] */

	u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */

				/*		0xc14~0xc17, 0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] */

	u32 rfRxAFE;		/* Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : */

				/*	0xc10~0xc13, 0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] */

	u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */

				/*	0xc80~0xc83, 0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] */

	u32 rfTxAFE;		/* Tx IQ DC Offset and Tx DFIR type */

				/*	0xc84~0xc87, 0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] */

	u32 rfLSSIReadBack;	/* LSSI RF readback data SI mode */

				/*	0x8a0~0x8af [16 bytes] */

	u32 rfLSSIReadBackPi;	/* LSSI RF readback data PI mode 0x8b8-8bc for Path A and B */

};



struct r_antenna_sel_ofdm {

	u32			r_tx_antenna:4;

	u32			r_ant_l:4;

	u32			r_ant_non_ht:4;

	u32			r_ant_ht1:4;

	u32			r_ant_ht2:4;

	u32			r_ant_ht_s1:4;

	u32			r_ant_non_ht_s1:4;

	u32			OFDM_TXSC:2;

	u32			Reserved:2;

};



struct r_antenna_sel_cck {

	u8			r_cckrx_enable_2:2;

	u8			r_cckrx_enable:2;

	u8			r_ccktx_enable:4;

};



/*------------------------------Define structure----------------------------*/





/*------------------------Export global variable----------------------------*/

/*------------------------Export global variable----------------------------*/





/*------------------------Export Macro Definition---------------------------*/

/*------------------------Export Macro Definition---------------------------*/





/*--------------------------Exported Function prototype---------------------*/

/*  */

/*  BB and RF register read/write */

/*  */

u32	PHY_QueryBBReg(struct rtw_adapter *Adapter, u32 RegAddr,

		       u32 BitMask);

void	PHY_SetBBReg(struct rtw_adapter *Adapter, u32 RegAddr,

		     u32 BitMask, u32 Data);

u32	PHY_QueryRFReg(struct rtw_adapter *Adapter,

		       enum RF_RADIO_PATH	eRFPath, u32 RegAddr,

		       u32 BitMask);

void	PHY_SetRFReg(struct rtw_adapter *Adapter,

		     enum RF_RADIO_PATH eRFPath, u32 RegAddr,

		     u32 BitMask,  u32	Data);



/*  */

/*  BB TX Power R/W */

/*  */

void PHY_SetTxPowerLevel8723A(struct rtw_adapter *Adapter, u8 channel);



/*  */

/*  Switch bandwidth for 8723A */

/*  */

void	PHY_SetBWMode23a8723A(struct rtw_adapter *pAdapter,

			   enum ht_channel_width ChnlWidth,

			   unsigned char Offset);



/*  */

/*  channel switch related funciton */

/*  */

void	PHY_SwChnl8723A(struct rtw_adapter *pAdapter, u8 channel);

				/*  Call after initialization */

void ChkFwCmdIoDone(struct rtw_adapter *Adapter);



/*  */

/*  Modify the value of the hw register when beacon interval be changed. */

/*  */

void

rtl8192c_PHY_SetBeaconHwReg(struct rtw_adapter *Adapter, u16 BeaconInterval);





void PHY_SwitchEphyParameter(struct rtw_adapter *Adapter);



void PHY_EnableHostClkReq(struct rtw_adapter *Adapter);



bool

SetAntennaConfig92C(struct rtw_adapter *Adapter, u8 DefaultAnt);



/*--------------------------Exported Function prototype---------------------*/



#define PHY_SetMacReg	PHY_SetBBReg



/* MAC/BB/RF HAL config */

int PHY_BBConfig8723A(struct rtw_adapter *Adapter);

int PHY_RFConfig8723A(struct rtw_adapter *Adapter);

s32 PHY_MACConfig8723A(struct rtw_adapter *padapter);



#endif

drivers/staging/rtl8723au/include/Hal8723APhyReg.h

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drivers/staging/rtl8723au/include/Hal8723PwrSeq.h

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#ifndef __HAL8723PWRSEQ_H__

#define __HAL8723PWRSEQ_H__

/*

	Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd

	There are 6 HW Power States:

	0: POFF--Power Off

	1: PDN--Power Down

	2: CARDEMU--Card Emulation

	3: ACT--Active Mode

	4: LPS--Low Power State

	5: SUS--Suspend



	The transision from different states are defined below

	TRANS_CARDEMU_TO_ACT

	TRANS_ACT_TO_CARDEMU

	TRANS_CARDEMU_TO_SUS

	TRANS_SUS_TO_CARDEMU

	TRANS_CARDEMU_TO_PDN

	TRANS_ACT_TO_LPS

	TRANS_LPS_TO_ACT



	TRANS_END

*/

#include "HalPwrSeqCmd.h"

#include "rtl8723a_spec.h"



#define	RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS	15

#define	RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS	15

#define	RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS	15

#define	RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS	15

#define	RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS	15

#define	RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS	15

#define	RTL8723A_TRANS_ACT_TO_LPS_STEPS	15

#define	RTL8723A_TRANS_LPS_TO_ACT_STEPS	15

#define	RTL8723A_TRANS_END_STEPS	1





/* format

 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },  comments here

 */

#define RTL8723A_TRANS_CARDEMU_TO_ACT														\

	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/   \

	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/	\

	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \

	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital , 1:isolation*/   \

	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]= 0*/	\

	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\

	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]= 1*/	\

	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]= 0*/	\

	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/	\

	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\

	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/	\

	{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 1},/*0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */\



#define RTL8723A_TRANS_ACT_TO_CARDEMU													\

	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\

	{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\

	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\

	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\

	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital , 1:isolation*/   \

	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/   \





#define RTL8723A_TRANS_CARDEMU_TO_SUS													\

	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\

	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\

	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \

	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \

	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\

	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\

	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/



#define RTL8723A_TRANS_SUS_TO_CARDEMU													\

	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\

	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\

	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\

	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \

	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/



#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS													\

	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\

	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\

	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/	\

	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \

	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \

	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\

	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/



#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU													\

	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\

	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\

	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\

	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/   \

	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\

	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \

	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/





#define RTL8723A_TRANS_CARDEMU_TO_PDN												\

	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \

	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \

	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\

	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/



#define RTL8723A_TRANS_PDN_TO_CARDEMU												\

	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/



#define RTL8723A_TRANS_ACT_TO_LPS														\

	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\

	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\

	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\

	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\

	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\

	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\

	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\

	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\

	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\

	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\

	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\

	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\

	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/



#define RTL8723A_TRANS_LPS_TO_ACT															\

	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\

	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\

	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\

	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\

	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\

	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]= 0  TSF in 40M*/\

	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\

	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\

	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\

	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\

	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/



#define RTL8723A_TRANS_END															\

	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},





extern struct wlan_pwr_cfg rtl8723AU_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS];

extern struct wlan_pwr_cfg rtl8723AU_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_END_STEPS];

extern struct wlan_pwr_cfg rtl8723AU_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];

extern struct wlan_pwr_cfg rtl8723AU_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];

extern struct wlan_pwr_cfg rtl8723AU_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS];

extern struct wlan_pwr_cfg rtl8723AU_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS];

extern struct wlan_pwr_cfg rtl8723AU_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];

extern struct wlan_pwr_cfg rtl8723AU_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS+RTL8723A_TRANS_END_STEPS];

extern struct wlan_pwr_cfg rtl8723AU_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS];



#endif

drivers/staging/rtl8723au/include/Hal8723UHWImg_CE.h

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#ifndef __INC_HAL8723U_FW_IMG_H

#define __INC_HAL8723U_FW_IMG_H



/*Created on  2013/01/14, 15:51*/



/* FW v16 enable usb interrupt */

#define Rtl8723UImgArrayLength 22172

extern u8 Rtl8723UFwImgArray[Rtl8723UImgArrayLength];

#define Rtl8723UBTImgArrayLength 1

extern u8 Rtl8723UFwBTImgArray[Rtl8723UBTImgArrayLength];



#define Rtl8723UUMCBCutImgArrayWithBTLength 24118

#define Rtl8723UUMCBCutImgArrayWithoutBTLength 19200



extern u8 Rtl8723UFwUMCBCutImgArrayWithBT[Rtl8723UUMCBCutImgArrayWithBTLength];

extern u8 Rtl8723UFwUMCBCutImgArrayWithoutBT[Rtl8723UUMCBCutImgArrayWithoutBTLength];



#define Rtl8723SUMCBCutMPImgArrayLength 24174

extern const u8 Rtl8723SFwUMCBCutMPImgArray[Rtl8723SUMCBCutMPImgArrayLength];



#define Rtl8723EBTImgArrayLength 15276

extern u8 Rtl8723EFwBTImgArray[Rtl8723EBTImgArrayLength] ;



#define Rtl8723UPHY_REG_Array_PGLength 336

extern u32 Rtl8723UPHY_REG_Array_PG[Rtl8723UPHY_REG_Array_PGLength];

#define Rtl8723UMACPHY_Array_PGLength 1

extern u32 Rtl8723UMACPHY_Array_PG[Rtl8723UMACPHY_Array_PGLength];



#endif /* ifndef __INC_HAL8723U_FW_IMG_H */

drivers/staging/rtl8723au/include/HalDMOutSrc8723A.h

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/******************************************************************************

 *

 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of version 2 of the GNU General Public License as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for

 * more details.

 *

 *

 ******************************************************************************/

#ifndef	__RTL8723A_ODM_H__

#define __RTL8723A_ODM_H__

/*  */



#define	RSSI_CCK	0

#define	RSSI_OFDM	1

#define	RSSI_DEFAULT	2



#define IQK_MAC_REG_NUM		4

#define IQK_ADDA_REG_NUM		16

#define IQK_BB_REG_NUM			9

#define HP_THERMAL_NUM		8





/*  */

/*  structure and define */

/*  */









/*------------------------Export global variable----------------------------*/

/*------------------------Export global variable----------------------------*/

/*------------------------Export Marco Definition---------------------------*/

/* define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;} */





/*  */

/*  function prototype */

/*  */



/*  */

/*  IQ calibrate */

/*  */

void rtl8723a_phy_iq_calibrate(struct rtw_adapter *pAdapter, bool bReCovery);



/*  */

/*  LC calibrate */

/*  */

void rtl8723a_phy_lc_calibrate(struct rtw_adapter *pAdapter);



/*  */

/*  AP calibrate */

/*  */

void rtl8723a_phy_ap_calibrate(struct rtw_adapter *pAdapter, char delta);



void rtl8723a_odm_check_tx_power_tracking(struct rtw_adapter *Adapter);



#endif

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