Commit 363de1d6 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-imx5-5.2' of... 

Merge tag 'clk-imx5-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx

Pull i.MX5 clk changes from Shawn Guo:

 - A couple of patches from Jonathan Neuschäfer to improve i.MX5 clock
   driver for i.MX50 support
 - Rename file clk-imx51-imx53.c to clk-imx5.c, as it covers support for
   all i.MX5 series SoCs including i.MX50

* tag 'clk-imx5-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  clk: imx: rename clk-imx51-imx53.c to clk-imx5.c
  clk: imx5: Fix i.MX50 ESDHC clock registers
  clk: imx5: Fix i.MX50 mainbus clock registers
parents 5d27e1cd de348df5

drivers/clk/imx/Makefile

+1 −1
Original line number Original line Diff line number Diff line
@@ -35,7 +35,7 @@ obj-$(CONFIG_SOC_IMX25) += clk-imx25.o 
obj-$(CONFIG_SOC_IMX27)  += clk-imx27.o

obj-$(CONFIG_SOC_IMX27)  += clk-imx27.o

obj-$(CONFIG_SOC_IMX31)  += clk-imx31.o

obj-$(CONFIG_SOC_IMX31)  += clk-imx31.o

obj-$(CONFIG_SOC_IMX35)  += clk-imx35.o

obj-$(CONFIG_SOC_IMX35)  += clk-imx35.o

obj-$(CONFIG_SOC_IMX5)   += clk-imx51-imx53.o

obj-$(CONFIG_SOC_IMX5)   += clk-imx5.o

obj-$(CONFIG_SOC_IMX6Q)  += clk-imx6q.o

obj-$(CONFIG_SOC_IMX6Q)  += clk-imx6q.o

obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o

obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o

obj-$(CONFIG_SOC_IMX6SLL) += clk-imx6sll.o

obj-$(CONFIG_SOC_IMX6SLL) += clk-imx6sll.o

drivers/clk/imx/clk-imx51-imx53.c→drivers/clk/imx/clk-imx5.c

+45 −14
Original line number Original line Diff line number Diff line
@@ -164,10 +164,6 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base) 
	clk[IMX5_CLK_CKIH1]		= imx_obtain_fixed_clock("ckih1", 0);

	clk[IMX5_CLK_CKIH1]		= imx_obtain_fixed_clock("ckih1", 0);

	clk[IMX5_CLK_CKIH2]		= imx_obtain_fixed_clock("ckih2", 0);

	clk[IMX5_CLK_CKIH2]		= imx_obtain_fixed_clock("ckih2", 0);





	clk[IMX5_CLK_PERIPH_APM]	= imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,

						periph_apm_sel, ARRAY_SIZE(periph_apm_sel));

	clk[IMX5_CLK_MAIN_BUS]		= imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,

						main_bus_sel, ARRAY_SIZE(main_bus_sel));

	clk[IMX5_CLK_PER_LP_APM]	= imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,

	clk[IMX5_CLK_PER_LP_APM]	= imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,

						per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));

						per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));

	clk[IMX5_CLK_PER_PRED1]		= imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);

	clk[IMX5_CLK_PER_PRED1]		= imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
@@ -191,16 +187,10 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base) 
	clk[IMX5_CLK_UART_PRED]		= imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);

	clk[IMX5_CLK_UART_PRED]		= imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);

	clk[IMX5_CLK_UART_ROOT]		= imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);

	clk[IMX5_CLK_UART_ROOT]		= imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);





	clk[IMX5_CLK_ESDHC_A_SEL]	= imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,

						standard_pll_sel, ARRAY_SIZE(standard_pll_sel));

	clk[IMX5_CLK_ESDHC_B_SEL]	= imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,

						standard_pll_sel, ARRAY_SIZE(standard_pll_sel));

	clk[IMX5_CLK_ESDHC_A_PRED]	= imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);

	clk[IMX5_CLK_ESDHC_A_PRED]	= imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);

	clk[IMX5_CLK_ESDHC_A_PODF]	= imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);

	clk[IMX5_CLK_ESDHC_A_PODF]	= imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);

	clk[IMX5_CLK_ESDHC_B_PRED]	= imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);

	clk[IMX5_CLK_ESDHC_B_PRED]	= imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);

	clk[IMX5_CLK_ESDHC_B_PODF]	= imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);

	clk[IMX5_CLK_ESDHC_B_PODF]	= imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);

	clk[IMX5_CLK_ESDHC_C_SEL]	= imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));

	clk[IMX5_CLK_ESDHC_D_SEL]	= imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));





	clk[IMX5_CLK_EMI_SEL]		= imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,

	clk[IMX5_CLK_EMI_SEL]		= imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,

						emi_slow_sel, ARRAY_SIZE(emi_slow_sel));

						emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
@@ -311,10 +301,6 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base) 
	clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");

	clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");

	clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);

	clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);





	/* Set SDHC parents to be PLL2 */

	clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);

	clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);



	/* move usb phy clk to 24MHz */

	/* move usb phy clk to 24MHz */

	clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]);

	clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]);

}

}
@@ -342,8 +328,21 @@ static void __init mx50_clocks_init(struct device_node *np) 




	mx5_clocks_common_init(ccm_base);

	mx5_clocks_common_init(ccm_base);





	/*

	 * This clock is called periph_clk in the i.MX50 Reference Manual, but

	 * it comes closest in scope to the main_bus_clk of i.MX51 and i.MX53

	 */

	clk[IMX5_CLK_MAIN_BUS]          = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 2,

						standard_pll_sel, ARRAY_SIZE(standard_pll_sel));



	clk[IMX5_CLK_LP_APM]		= imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,

	clk[IMX5_CLK_LP_APM]		= imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,

						lp_apm_sel, ARRAY_SIZE(lp_apm_sel));

						lp_apm_sel, ARRAY_SIZE(lp_apm_sel));

	clk[IMX5_CLK_ESDHC_A_SEL]	= imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 21, 2,

						standard_pll_sel, ARRAY_SIZE(standard_pll_sel));

	clk[IMX5_CLK_ESDHC_B_SEL]	= imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,

						standard_pll_sel, ARRAY_SIZE(standard_pll_sel));

	clk[IMX5_CLK_ESDHC_C_SEL]	= imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 20, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));

	clk[IMX5_CLK_ESDHC_D_SEL]	= imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));

	clk[IMX5_CLK_ESDHC1_PER_GATE]	= imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);

	clk[IMX5_CLK_ESDHC1_PER_GATE]	= imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);

	clk[IMX5_CLK_ESDHC2_PER_GATE]	= imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);

	clk[IMX5_CLK_ESDHC2_PER_GATE]	= imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);

	clk[IMX5_CLK_ESDHC3_PER_GATE]	= imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);

	clk[IMX5_CLK_ESDHC3_PER_GATE]	= imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
@@ -372,6 +371,10 @@ static void __init mx50_clocks_init(struct device_node *np) 
	clk_data.clk_num = ARRAY_SIZE(clk);

	clk_data.clk_num = ARRAY_SIZE(clk);

	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);

	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);





	/* Set SDHC parents to be PLL2 */

	clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);

	clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);



	/* set SDHC root clock to 200MHZ*/

	/* set SDHC root clock to 200MHZ*/

	clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);

	clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);

	clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);

	clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
@@ -410,6 +413,10 @@ static void __init mx51_clocks_init(struct device_node *np) 




	mx5_clocks_common_init(ccm_base);

	mx5_clocks_common_init(ccm_base);





	clk[IMX5_CLK_PERIPH_APM]	= imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,

						periph_apm_sel, ARRAY_SIZE(periph_apm_sel));

	clk[IMX5_CLK_MAIN_BUS]		= imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,

						main_bus_sel, ARRAY_SIZE(main_bus_sel));

	clk[IMX5_CLK_LP_APM]		= imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,

	clk[IMX5_CLK_LP_APM]		= imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,

						lp_apm_sel, ARRAY_SIZE(lp_apm_sel));

						lp_apm_sel, ARRAY_SIZE(lp_apm_sel));

	clk[IMX5_CLK_IPU_DI0_SEL]	= imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,

	clk[IMX5_CLK_IPU_DI0_SEL]	= imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
@@ -422,6 +429,12 @@ static void __init mx51_clocks_init(struct device_node *np) 
						mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));

						mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));

	clk[IMX5_CLK_TVE_GATE]		= imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);

	clk[IMX5_CLK_TVE_GATE]		= imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);

	clk[IMX5_CLK_TVE_PRED]		= imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);

	clk[IMX5_CLK_TVE_PRED]		= imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);

	clk[IMX5_CLK_ESDHC_A_SEL]	= imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,

						standard_pll_sel, ARRAY_SIZE(standard_pll_sel));

	clk[IMX5_CLK_ESDHC_B_SEL]	= imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,

						standard_pll_sel, ARRAY_SIZE(standard_pll_sel));

	clk[IMX5_CLK_ESDHC_C_SEL]	= imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));

	clk[IMX5_CLK_ESDHC_D_SEL]	= imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));

	clk[IMX5_CLK_ESDHC1_PER_GATE]	= imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);

	clk[IMX5_CLK_ESDHC1_PER_GATE]	= imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);

	clk[IMX5_CLK_ESDHC2_PER_GATE]	= imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);

	clk[IMX5_CLK_ESDHC2_PER_GATE]	= imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);

	clk[IMX5_CLK_ESDHC3_PER_GATE]	= imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);

	clk[IMX5_CLK_ESDHC3_PER_GATE]	= imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
@@ -452,6 +465,10 @@ static void __init mx51_clocks_init(struct device_node *np) 
	/* set the usboh3 parent to pll2_sw */

	/* set the usboh3 parent to pll2_sw */

	clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);

	clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);





	/* Set SDHC parents to be PLL2 */

	clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);

	clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);



	/* set SDHC root clock to 166.25MHZ*/

	/* set SDHC root clock to 166.25MHZ*/

	clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);

	clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);

	clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);

	clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
@@ -506,6 +523,10 @@ static void __init mx53_clocks_init(struct device_node *np) 




	mx5_clocks_common_init(ccm_base);

	mx5_clocks_common_init(ccm_base);





	clk[IMX5_CLK_PERIPH_APM]	= imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,

						periph_apm_sel, ARRAY_SIZE(periph_apm_sel));

	clk[IMX5_CLK_MAIN_BUS]		= imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,

						main_bus_sel, ARRAY_SIZE(main_bus_sel));

	clk[IMX5_CLK_LP_APM]		= imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,

	clk[IMX5_CLK_LP_APM]		= imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,

						lp_apm_sel, ARRAY_SIZE(lp_apm_sel));

						lp_apm_sel, ARRAY_SIZE(lp_apm_sel));

	clk[IMX5_CLK_LDB_DI1_DIV_3_5]	= imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);

	clk[IMX5_CLK_LDB_DI1_DIV_3_5]	= imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
@@ -527,6 +548,12 @@ static void __init mx53_clocks_init(struct device_node *np) 
						mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);

						mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);

	clk[IMX5_CLK_TVE_GATE]		= imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);

	clk[IMX5_CLK_TVE_GATE]		= imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);

	clk[IMX5_CLK_TVE_PRED]		= imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);

	clk[IMX5_CLK_TVE_PRED]		= imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);

	clk[IMX5_CLK_ESDHC_A_SEL]	= imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,

						standard_pll_sel, ARRAY_SIZE(standard_pll_sel));

	clk[IMX5_CLK_ESDHC_B_SEL]	= imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,

						standard_pll_sel, ARRAY_SIZE(standard_pll_sel));

	clk[IMX5_CLK_ESDHC_C_SEL]	= imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));

	clk[IMX5_CLK_ESDHC_D_SEL]	= imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));

	clk[IMX5_CLK_ESDHC1_PER_GATE]	= imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);

	clk[IMX5_CLK_ESDHC1_PER_GATE]	= imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);

	clk[IMX5_CLK_ESDHC2_PER_GATE]	= imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);

	clk[IMX5_CLK_ESDHC2_PER_GATE]	= imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);

	clk[IMX5_CLK_ESDHC3_PER_GATE]	= imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);

	clk[IMX5_CLK_ESDHC3_PER_GATE]	= imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
@@ -589,6 +616,10 @@ static void __init mx53_clocks_init(struct device_node *np) 
	clk_data.clk_num = ARRAY_SIZE(clk);

	clk_data.clk_num = ARRAY_SIZE(clk);

	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);

	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);





	/* Set SDHC parents to be PLL2 */

	clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);

	clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);



	/* set SDHC root clock to 200MHZ*/

	/* set SDHC root clock to 200MHZ*/

	clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);

	clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);

	clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);

	clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);

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