Commit 35d782fe authored by Chunming Zhou's avatar Chunming Zhou Committed by Alex Deucher
Browse files

drm/amdgpu: add amdgpu soft reset



Check gpu status first, if MC/VMC/DISPLAY hang, directly triger full reset.
If engine hangs, then triger engine soft reset, if soft reset fails, will
fallback to full reset.

Signed-off-by: default avatarChunming Zhou <David1.Zhou@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1057f20c
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+86 −18
Original line number Diff line number Diff line
@@ -1962,7 +1962,8 @@ int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
	for (i = 0; i < adev->num_ip_blocks; i++) {
		if (!adev->ip_block_status[i].valid)
			continue;
		if (adev->ip_blocks[i].funcs->pre_soft_reset) {
		if (adev->ip_block_status[i].hang &&
		    adev->ip_blocks[i].funcs->pre_soft_reset) {
			r = adev->ip_blocks[i].funcs->pre_soft_reset(adev);
			if (r)
				return r;
@@ -1972,6 +1973,58 @@ int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
	return 0;
}

static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
{
	if (adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang ||
	    adev->ip_block_status[AMD_IP_BLOCK_TYPE_IH].hang ||
	    adev->ip_block_status[AMD_IP_BLOCK_TYPE_SMC].hang ||
	    adev->ip_block_status[AMD_IP_BLOCK_TYPE_GFX].hang ||
	    adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang ||
	    adev->ip_block_status[AMD_IP_BLOCK_TYPE_UVD].hang ||
	    adev->ip_block_status[AMD_IP_BLOCK_TYPE_VCE].hang ||
	    adev->ip_block_status[AMD_IP_BLOCK_TYPE_ACP].hang ||
	    adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang) {
		DRM_INFO("Some block need full reset!\n");
		return true;
	}
	return false;
}

static int amdgpu_soft_reset(struct amdgpu_device *adev)
{
	int i, r = 0;

	for (i = 0; i < adev->num_ip_blocks; i++) {
		if (!adev->ip_block_status[i].valid)
			continue;
		if (adev->ip_block_status[i].hang &&
		    adev->ip_blocks[i].funcs->soft_reset) {
			r = adev->ip_blocks[i].funcs->soft_reset(adev);
			if (r)
				return r;
		}
	}

	return 0;
}

static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
{
	int i, r = 0;

	for (i = 0; i < adev->num_ip_blocks; i++) {
		if (!adev->ip_block_status[i].valid)
			continue;
		if (adev->ip_block_status[i].hang &&
		    adev->ip_blocks[i].funcs->post_soft_reset)
			r = adev->ip_blocks[i].funcs->post_soft_reset(adev);
		if (r)
			return r;
	}

	return 0;
}

/**
 * amdgpu_gpu_reset - reset the asic
 *
@@ -1984,6 +2037,7 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
{
	int i, r;
	int resched;
	bool need_full_reset;

	if (!amdgpu_check_soft_reset(adev)) {
		DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
@@ -2007,6 +2061,19 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
	/* after all hw jobs are reset, hw fence is meaningless, so force_completion */
	amdgpu_fence_driver_force_completion(adev);

	need_full_reset = amdgpu_need_full_reset(adev);

	if (!need_full_reset) {
		amdgpu_pre_soft_reset(adev);
		r = amdgpu_soft_reset(adev);
		amdgpu_post_soft_reset(adev);
		if (r || amdgpu_check_soft_reset(adev)) {
			DRM_INFO("soft reset failed, will fallback to full reset!\n");
			need_full_reset = true;
		}
	}

	if (need_full_reset) {
		/* save scratch */
		amdgpu_atombios_scratch_regs_save(adev);
		r = amdgpu_suspend(adev);
@@ -2029,6 +2096,7 @@ retry:
		}
		/* restore scratch */
		amdgpu_atombios_scratch_regs_restore(adev);
	}
	if (!r) {
		r = amdgpu_ib_ring_tests(adev);
		if (r) {
+2 −0
Original line number Diff line number Diff line
@@ -165,6 +165,8 @@ struct amd_ip_funcs {
	int (*pre_soft_reset)(void *handle);
	/* soft reset the IP block */
	int (*soft_reset)(void *handle);
	/* post soft reset the IP block */
	int (*post_soft_reset)(void *handle);
	/* enable/disable cg for the IP block */
	int (*set_clockgating_state)(void *handle,
				     enum amd_clockgating_state state);