Commit 35c32f20 authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher
Browse files

drm/amd/amdgpu: Tidy up register list formatting. 



Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fd8bf087

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+64 −32
Original line number Diff line number Diff line
@@ -66,38 +66,70 @@ MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); 


static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =

{

	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),

		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)},

	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),

		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)},

	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),

		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)},

	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),

		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)},

	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),

		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)},

	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),

		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)},

	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),

		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)},

	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),

		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)},

	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),

		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)},

	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),

		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)},

	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),

		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)},

	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),

	       	SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)},

	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),

		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},

	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),

		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)},

	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),

		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)},

	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),

		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)}

	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) },

	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) },

	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) },

	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) },

	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) },

	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) },

	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) },

	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) },

	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) },

	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) },

	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10) },

	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11) },

	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},

	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13) },

	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14) },

	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15),

	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15) }

};



static const u32 golden_settings_gc_9_0[] =

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