Commit 35a86976 authored by Catalin Marinas's avatar Catalin Marinas
Browse files

arm64: Update the TCR_EL1 translation granule definitions for 16K pages 



The current TCR register setting in arch/arm64/mm/proc.S assumes that
TCR_EL1.TG* fields are one bit wide and bit 31 is RES1 (reserved, set to
1). With the addition of 16K pages (currently unsupported in the
kernel), the TCR_EL1.TG* fields have been extended to two bits. This
patch updates the corresponding Linux definitions and drops the bit 31
setting in proc.S in favour of the new macros.

Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Reported-by: default avatarJoe Sylve <joe.sylve@gmail.com>
parent 33648de0

arch/arm64/include/asm/pgtable-hwdef.h

+5 −1
Original line number Diff line number Diff line
@@ -120,8 +120,12 @@ 
#define TCR_ORGN_WBnWA		((UL(3) << 10) | (UL(3) << 26))

#define TCR_ORGN_MASK		((UL(3) << 10) | (UL(3) << 26))

#define TCR_SHARED		((UL(3) << 12) | (UL(3) << 28))

#define TCR_TG0_4K		(UL(0) << 14)

#define TCR_TG0_64K		(UL(1) << 14)

#define TCR_TG1_64K		(UL(1) << 30)

#define TCR_TG0_16K		(UL(2) << 14)

#define TCR_TG1_16K		(UL(1) << 30)

#define TCR_TG1_4K		(UL(2) << 30)

#define TCR_TG1_64K		(UL(3) << 30)

#define TCR_ASID16		(UL(1) << 36)

#define TCR_TBI0		(UL(1) << 37)

arch/arm64/mm/proc.S

+14 −11
Original line number Diff line number Diff line
@@ -28,14 +28,21 @@ 


#include "proc-macros.S"



#ifndef CONFIG_SMP

/* PTWs cacheable, inner/outer WBWA not shareable */

#define TCR_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA

#ifdef CONFIG_ARM64_64K_PAGES

#define TCR_TG_FLAGS	TCR_TG0_64K | TCR_TG1_64K

#else

#define TCR_TG_FLAGS	TCR_TG0_4K | TCR_TG1_4K

#endif



#ifdef CONFIG_SMP

#define TCR_SMP_FLAGS	TCR_SHARED

#else

/* PTWs cacheable, inner/outer WBWA shareable */

#define TCR_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA | TCR_SHARED

#define TCR_SMP_FLAGS	0

#endif



/* PTWs cacheable, inner/outer WBWA */

#define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA



#define MAIR(attr, mt)	((attr) << ((mt) * 8))



/*
@@ -209,18 +216,14 @@ ENTRY(__cpu_setup) 
	 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for

	 * both user and kernel.

	 */

	ldr	x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | \

		      TCR_ASID16 | TCR_TBI0 | (1 << 31)

	ldr	x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \

			TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0

	/*

	 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in

	 * TCR_EL1.

	 */

	mrs	x9, ID_AA64MMFR0_EL1

	bfi	x10, x9, #32, #3

#ifdef CONFIG_ARM64_64K_PAGES

	orr	x10, x10, TCR_TG0_64K

	orr	x10, x10, TCR_TG1_64K

#endif

	msr	tcr_el1, x10

	ret					// return to head.S

ENDPROC(__cpu_setup)

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