MIPS: R5000: Fix TLB hazard handling. (359187d6) · Commits · 戴 / test

R5000 and the Nevada CPUs (RM5230, RM5231, RM5260, RM5261, RM5270 and RM5271) are basically the same CPU core and all are documented to require two instructions separating a write to c0_pagemask, c0_entryhi, c0_entrylo0, c0_entrylo1 or c0_index. So far we were only providing on cycle before / after a TLBR/TLBWI for R5000 but 3 cycles before and 1 cycles after for the Nevadas. Signed-off-by:

Ralf Baechle <ralf@linux-mips.org>

arch/mips/mm/tlbex.c

+8 −15

Original line number	Diff line number	Diff line
		@@ -511,13 +511,19 @@ static void __cpuinit build_tlb_write_entry(u32 p, struct uasm_label l,

		case CPU_R4600:
		case CPU_R4700:
		case CPU_R5000:
		case CPU_R5000A:
		uasm_i_nop(p);
		tlbw(p);
		uasm_i_nop(p);
		break;

		case CPU_R5000:
		case CPU_R5000A:
		case CPU_NEVADA:
		uasm_i_nop(p); /* QED specifies 2 nops hazard */
		uasm_i_nop(p); /* QED specifies 2 nops hazard */
		tlbw(p);
		break;

		case CPU_R4300:
		case CPU_5KC:
		case CPU_TX49XX:
		@@ -551,19 +557,6 @@ static void __cpuinit build_tlb_write_entry(u32 p, struct uasm_label l,
		tlbw(p);
		break;

		case CPU_NEVADA:
		uasm_i_nop(p); /* QED specifies 2 nops hazard */
		uasm_i_nop(p); /* QED specifies 2 nops hazard */
		/*
		* This branch uses up a mtc0 hazard nop slot and saves
		* a nop after the tlbw instruction.
		*/
		uasm_bgezl_hazard(p, r, hazard_instance);
		tlbw(p);
		uasm_bgezl_label(l, p, hazard_instance);
		hazard_instance++;
		break;

		case CPU_RM7000:
		uasm_i_nop(p);
		uasm_i_nop(p);

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