crypto: caam - enable prediction resistance in HRWNG (358ba762) · Commits · 戴 / test

drivers/crypto/caam/Kconfig

+1 −0

Original line number	Diff line number	Diff line
		@@ -13,6 +13,7 @@ config CRYPTO_DEV_FSL_CAAM
		depends on FSL_SOC \|\| ARCH_MXC \|\| ARCH_LAYERSCAPE
		select SOC_BUS
		select CRYPTO_DEV_FSL_CAAM_COMMON
		imply FSL_MC_BUS
		help
		Enables the driver module for Freescale's Cryptographic Accelerator
		and Assurance Module (CAAM), also known as the SEC version 4 (SEC4).

drivers/crypto/caam/caamrng.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -69,7 +69,8 @@ static u32 caam_init_desc(u32 desc, dma_addr_t dst_dma, int len)
		{
		init_job_desc(desc, 0); /* + 1 cmd_sz */
		/* Generate random bytes: + 1 cmd_sz */
		append_operation(desc, OP_ALG_ALGSEL_RNG \| OP_TYPE_CLASS1_ALG);
		append_operation(desc, OP_ALG_ALGSEL_RNG \| OP_TYPE_CLASS1_ALG \|
		OP_ALG_PR_ON);
		/* Store bytes: + 1 cmd_sz + caam_ptr_sz */
		append_fifo_store(desc, dst_dma, len, FIFOST_TYPE_RNGSTORE);

drivers/crypto/caam/ctrl.c

+60 −13

Original line number	Diff line number	Diff line
		@@ -10,6 +10,7 @@
		#include <linux/of_address.h>
		#include <linux/of_irq.h>
		#include <linux/sys_soc.h>
		#include <linux/fsl/mc.h>

		#include "compat.h"
		#include "regs.h"
		@@ -36,7 +37,8 @@ static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
		init_job_desc(desc, 0);

		op_flags = OP_TYPE_CLASS1_ALG \| OP_ALG_ALGSEL_RNG \|
		(handle << OP_ALG_AAI_SHIFT) \| OP_ALG_AS_INIT;
		(handle << OP_ALG_AAI_SHIFT) \| OP_ALG_AS_INIT \|
		OP_ALG_PR_ON;

		/* INIT RNG in non-test mode */
		append_operation(desc, op_flags);
		@@ -278,13 +280,26 @@ static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
		return -ENOMEM;

		for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
		const u32 rdsta_if = RDSTA_IF0 << sh_idx;
		const u32 rdsta_pr = RDSTA_PR0 << sh_idx;
		const u32 rdsta_mask = rdsta_if \| rdsta_pr;
		/*
		* If the corresponding bit is set, this state handle
		* was initialized by somebody else, so it's left alone.
		*/
		if ((1 << sh_idx) & state_handle_mask)
		if (rdsta_if & state_handle_mask) {
		if (rdsta_pr & state_handle_mask)
		continue;

		dev_info(ctrldev,
		"RNG4 SH%d was previously instantiated without prediction resistance. Tearing it down\n",
		sh_idx);

		ret = deinstantiate_rng(ctrldev, rdsta_if);
		if (ret)
		break;
		}

		/* Create the descriptor for instantiating RNG State Handle */
		build_instantiation_desc(desc, sh_idx, gen_sk);

		@@ -303,9 +318,9 @@ static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
		if (ret)
		break;

		rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
		rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;
		if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) \|\|
		!(rdsta_val & (1 << sh_idx))) {
		(rdsta_val & rdsta_mask) != rdsta_mask) {
		ret = -EAGAIN;
		break;
		}
		@@ -564,6 +579,26 @@ static void caam_remove_debugfs(void *root)
		}
		#endif

		#ifdef CONFIG_FSL_MC_BUS
		static bool check_version(struct fsl_mc_version *mc_version, u32 major,
		u32 minor, u32 revision)
		{
		if (mc_version->major > major)
		return true;

		if (mc_version->major == major) {
		if (mc_version->minor > minor)
		return true;

		if (mc_version->minor == minor &&
		mc_version->revision > revision)
		return true;
		}

		return false;
		}
		#endif

		/* Probe routine for CAAM top (controller) level */
		static int caam_probe(struct platform_device *pdev)
		{
		@@ -582,6 +617,7 @@ static int caam_probe(struct platform_device *pdev)
		u8 rng_vid;
		int pg_size;
		int BLOCK_OFFSET = 0;
		bool pr_support = false;

		ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
		if (!ctrlpriv)
		@@ -667,6 +703,21 @@ static int caam_probe(struct platform_device *pdev)

		/* Get the IRQ of the controller (for security violations only) */
		ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
		np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc");
		ctrlpriv->mc_en = !!np;
		of_node_put(np);

		#ifdef CONFIG_FSL_MC_BUS
		if (ctrlpriv->mc_en) {
		struct fsl_mc_version *mc_version;

		mc_version = fsl_mc_get_version();
		if (mc_version)
		pr_support = check_version(mc_version, 10, 20, 0);
		else
		return -EPROBE_DEFER;
		}
		#endif

		/*
		* Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
		@@ -674,10 +725,6 @@ static int caam_probe(struct platform_device *pdev)
		* In case of SoCs with Management Complex, MC f/w performs
		* the configuration.
		*/
		np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc");
		ctrlpriv->mc_en = !!np;
		of_node_put(np);

		if (!ctrlpriv->mc_en)
		clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK,
		MCFGR_AWCACHE_CACH \| MCFGR_AWCACHE_BUFF \|
		@@ -784,7 +831,7 @@ static int caam_probe(struct platform_device *pdev)
		* already instantiated, do RNG instantiation
		* In case of SoCs with Management Complex, RNG is managed by MC f/w.
		*/
		if (!ctrlpriv->mc_en && rng_vid >= 4) {
		if (!(ctrlpriv->mc_en && pr_support) && rng_vid >= 4) {
		ctrlpriv->rng4_sh_init =
		rd_reg32(&ctrl->r4tst[0].rdsta);
		/*
		@@ -794,11 +841,11 @@ static int caam_probe(struct platform_device *pdev)
		* to regenerate these keys before the next POR.
		*/
		gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
		ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
		ctrlpriv->rng4_sh_init &= RDSTA_MASK;
		do {
		int inst_handles =
		rd_reg32(&ctrl->r4tst[0].rdsta) &
		RDSTA_IFMASK;
		RDSTA_MASK;
		/*
		* If either SH were instantiated by somebody else
		* (e.g. u-boot) then it is assumed that the entropy
		@@ -838,7 +885,7 @@ static int caam_probe(struct platform_device *pdev)
		* Set handles init'ed by this module as the complement of the
		* already initialized ones
		*/
		ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
		ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_MASK;

		/* Enable RDB bit so that RNG works faster */
		clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);

drivers/crypto/caam/desc.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -1254,6 +1254,8 @@
		#define OP_ALG_ICV_OFF (0 << OP_ALG_ICV_SHIFT)
		#define OP_ALG_ICV_ON (1 << OP_ALG_ICV_SHIFT)

		#define OP_ALG_PR_ON BIT(1)

		#define OP_ALG_DIR_SHIFT 0
		#define OP_ALG_DIR_MASK 1
		#define OP_ALG_DECRYPT 0

drivers/crypto/caam/regs.h

+3 −1

Original line number	Diff line number	Diff line
		@@ -524,9 +524,11 @@ struct rng4tst {
		u32 rsvd1[40];
		#define RDSTA_SKVT 0x80000000
		#define RDSTA_SKVN 0x40000000
		#define RDSTA_PR0 BIT(4)
		#define RDSTA_PR1 BIT(5)
		#define RDSTA_IF0 0x00000001
		#define RDSTA_IF1 0x00000002
		#define RDSTA_IFMASK (RDSTA_IF1 \| RDSTA_IF0)
		#define RDSTA_MASK (RDSTA_PR1 \| RDSTA_PR0 \| RDSTA_IF1 \| RDSTA_IF0)
		u32 rdsta;
		u32 rsvd2[15];
		};

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