Commit 35891d40 authored by Michael Ellerman's avatar Michael Ellerman
Browse files

Merge remote-tracking branch 'scottwood/next' into next 

Scott says:

"Highlights include a bunch of 8xx optimizations, device tree bindings
for Freescale BMan, QMan, and FMan datapath components, misc device tree
updates, and inbound rio window support."
parents 80fa93fc 76f3e292

Documentation/devicetree/bindings/clock/qoriq-clock.txt

+12 −2
Original line number Diff line number Diff line
@@ -62,6 +62,8 @@ Required properties: 
		It takes parent's clock-frequency as its clock.

	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).

		It takes parent's clock-frequency as its clock.

	* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)

	* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)

- #clock-cells: From common clock binding. The number of cells in a

	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"

	clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
@@ -128,8 +130,16 @@ Example for clock block and clock provider: 
			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";

			clock-output-names = "cmux1";

		};



		platform-pll: platform-pll@c00 {

			#clock-cells = <1>;

			reg = <0xc00 0x4>;

			compatible = "fsl,qoriq-platform-pll-1.0";

			clocks = <&sysclk>;

			clock-output-names = "platform-pll", "platform-pll-div2";

		};

	};

};

  }



Example for clock consumer:
@@ -139,4 +149,4 @@ Example for clock consumer: 
		clocks = <&mux0>;

		...

	};

  }
 
};

Documentation/devicetree/bindings/powerpc/fsl/fman.txt

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=============================================================================

Freescale Frame Manager Device Bindings



CONTENTS

  - FMan Node

  - FMan Port Node

  - FMan MURAM Node

  - FMan dTSEC/XGEC/mEMAC Node

  - FMan IEEE 1588 Node

  - Example



=============================================================================

FMan Node



DESCRIPTION



Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,

etc.) the FMan node will have child nodes for each of them.



PROPERTIES



- compatible

		Usage: required

		Value type: <stringlist>

		Definition: Must include "fsl,fman"

		FMan version can be determined via FM_IP_REV_1 register in the

		FMan block. The offset is 0xc4 from the beginning of the

		Frame Processing Manager memory map (0xc3000 from the

		beginning of the FMan node).



- cell-index

		Usage: required

		Value type: <u32>

		Definition: Specifies the index of the FMan unit.



		The cell-index value may be used by the SoC, to identify the

		FMan unit in the SoC memory map. In the table bellow,

		there's a description of the cell-index use in each SoC:



		- P1023:

		register[bit]			FMan unit	cell-index

		============================================================

		DEVDISR[1]			1		0



		- P2041, P3041, P4080 P5020, P5040:

		register[bit]			FMan unit	cell-index

		============================================================

		DCFG_DEVDISR2[6]		1		0

		DCFG_DEVDISR2[14]		2		1

			(Second FM available only in P4080 and P5040)



		- B4860, T1040, T2080, T4240:

		register[bit]			FMan unit	cell-index

		============================================================

		DCFG_CCSR_DEVDISR2[24]		1		0

		DCFG_CCSR_DEVDISR2[25]		2		1

			(Second FM available only in T4240)



		DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in

		the specific SoC "Device Configuration/Pin Control" Memory

		Map.



- reg

		Usage: required

		Value type: <prop-encoded-array>

		Definition: A standard property. Specifies the offset of the

		following configuration registers:

		- BMI configuration registers.

		- QMI configuration registers.

		- DMA configuration registers.

		- FPM configuration registers.

		- FMan controller configuration registers.



- ranges

		Usage: required

		Value type: <prop-encoded-array>

		Definition: A standard property.



- clocks

		Usage: required

		Value type: <prop-encoded-array>

		Definition: phandle for the fman input clock.



- clock-names

		usage: required

		Value type: <stringlist>

		Definition: "fmanclk" for the fman input clock.



- interrupts

		Usage: required

		Value type: <prop-encoded-array>

		Definition: A pair of IRQs are specified in this property.

		The first element is associated with the event interrupts and

		the second element is associated with the error interrupts.



- fsl,qman-channel-range

		Usage: required

		Value type: <prop-encoded-array>

		Definition: Specifies the range of the available dedicated

		channels in the FMan. The first cell specifies the beginning

		of the range and the second cell specifies the number of

		channels.

		Further information available at:

		"Work Queue (WQ) Channel Assignments in the QMan" section

		in DPAA Reference Manual.



- fsl,qman

- fsl,bman

		Usage: required

		Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt



=============================================================================

FMan MURAM Node



DESCRIPTION



FMan Internal memory - shared between all the FMan modules.

It contains data structures that are common and written to or read by

the modules.

FMan internal memory is split into the following parts:

	Packet buffering (Tx/Rx FIFOs)

	Frames internal context



PROPERTIES



- compatible

		Usage: required

		Value type: <stringlist>

		Definition: Must include "fsl,fman-muram"



- ranges

		Usage: required

		Value type: <prop-encoded-array>

		Definition: A standard property.

		Specifies the multi-user memory offset and the size within

		the FMan.



EXAMPLE



muram@0 {

	compatible = "fsl,fman-muram";

	ranges = <0 0x000000 0x28000>;

};



=============================================================================

FMan Port Node



DESCRIPTION



The Frame Manager (FMan) supports several types of hardware ports:

	Ethernet receiver (RX)

	Ethernet transmitter (TX)

	Offline/Host command (O/H)



PROPERTIES



- compatible

		Usage: required

		Value type: <stringlist>

		Definition: A standard property.

		Must include one of the following:

			- "fsl,fman-v2-port-oh" for FManV2 OH ports

			- "fsl,fman-v2-port-rx" for FManV2 RX ports

			- "fsl,fman-v2-port-tx" for FManV2 TX ports

			- "fsl,fman-v3-port-oh" for FManV3 OH ports

			- "fsl,fman-v3-port-rx" for FManV3 RX ports

			- "fsl,fman-v3-port-tx" for FManV3 TX ports



- cell-index

		Usage: required

		Value type: <u32>

		Definition: Specifies the hardware port id.

		Each hardware port on the FMan has its own hardware PortID.

		Super set of all hardware Port IDs available at FMan Reference

		Manual under "FMan Hardware Ports in Freescale Devices" table.



		Each hardware port is assigned a 4KB, port-specific page in

		the FMan hardware port memory region (which is part of the

		FMan memory map). The first 4 KB in the FMan hardware ports

		memory region is used for what are called common registers.

		The subsequent 63 4KB pages are allocated to the hardware

		ports.

		The page of a specific port is determined by the cell-index.



- reg

		Usage: required

		Value type: <prop-encoded-array>

		Definition: There is one reg region describing the port

		configuration registers.



EXAMPLE



port@a8000 {

	cell-index = <0x28>;

	compatible = "fsl,fman-v2-port-tx";

	reg = <0xa8000 0x1000>;

};



port@88000 {

	cell-index = <0x8>;

	compatible = "fsl,fman-v2-port-rx";

	reg = <0x88000 0x1000>;

};



port@81000 {

	cell-index = <0x1>;

	compatible = "fsl,fman-v2-port-oh";

	reg = <0x81000 0x1000>;

};



=============================================================================

FMan dTSEC/XGEC/mEMAC Node



DESCRIPTION



mEMAC/dTSEC/XGEC are the Ethernet network interfaces



PROPERTIES



- compatible

		Usage: required

		Value type: <stringlist>

		Definition: A standard property.

		Must include one of the following:

		- "fsl,fman-dtsec" for dTSEC MAC

		- "fsl,fman-xgec" for XGEC MAC

		- "fsl,fman-memac for mEMAC MAC



- cell-index

		Usage: required

		Value type: <u32>

		Definition: Specifies the MAC id.



		The cell-index value may be used by the FMan or the SoC, to

		identify the MAC unit in the FMan (or SoC) memory map.

		In the tables bellow there's a description of the cell-index

		use, there are two tables, one describes the use of cell-index

		by the FMan, the second describes the use by the SoC:



		1. FMan Registers



		FManV2:

		register[bit]		MAC		cell-index

		============================================================

		FM_EPI[16]		XGEC		8

		FM_EPI[16+n]		dTSECn		n-1

		FM_NPI[11+n]		dTSECn		n-1

			n = 1,..,5



		FManV3:

		register[bit]		MAC		cell-index

		============================================================

		FM_EPI[16+n]		mEMACn		n-1

		FM_EPI[25]		mEMAC10		9



		FM_NPI[11+n]		mEMACn		n-1

		FM_NPI[10]		mEMAC10		9

		FM_NPI[11]		mEMAC9		8

			n = 1,..8



		FM_EPI and FM_NPI are located in the FMan memory map.



		2. SoC registers:



		- P2041, P3041, P4080 P5020, P5040:

		register[bit]		FMan		MAC		cell

					Unit				index

		============================================================

		DCFG_DEVDISR2[7]	1		XGEC		8

		DCFG_DEVDISR2[7+n]	1		dTSECn		n-1

		DCFG_DEVDISR2[15]	2		XGEC		8

		DCFG_DEVDISR2[15+n]	2		dTSECn		n-1

			n = 1,..5



		- T1040, T2080, T4240, B4860:

		register[bit]			FMan	MAC		cell

						Unit			index

		============================================================

		DCFG_CCSR_DEVDISR2[n-1]		1	mEMACn		n-1

		DCFG_CCSR_DEVDISR2[11+n]	2	mEMACn		n-1

			n = 1,..6,9,10



		EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in

		the specific SoC "Device Configuration/Pin Control" Memory

		Map.



- reg

		Usage: required

		Value type: <prop-encoded-array>

		Definition: A standard property.



- fsl,fman-ports

		Usage: required

		Value type: <prop-encoded-array>

		Definition: An array of two phandles - the first references is

		the FMan RX port and the second is the TX port used by this

		MAC.



- ptp-timer

		Usage required

		Value type: <phandle>

		Definition: A phandle for 1EEE1588 timer.



EXAMPLE



fman1_tx28: port@a8000 {

	cell-index = <0x28>;

	compatible = "fsl,fman-v2-port-tx";

	reg = <0xa8000 0x1000>;

};



fman1_rx8: port@88000 {

	cell-index = <0x8>;

	compatible = "fsl,fman-v2-port-rx";

	reg = <0x88000 0x1000>;

};



ptp-timer: ptp_timer@fe000 {

	compatible = "fsl,fman-ptp-timer";

	reg = <0xfe000 0x1000>;

};



ethernet@e0000 {

	compatible = "fsl,fman-dtsec";

	cell-index = <0>;

	reg = <0xe0000 0x1000>;

	fsl,fman-ports = <&fman1_rx8 &fman1_tx28>;

	ptp-timer = <&ptp-timer>;

};



============================================================================

FMan IEEE 1588 Node



DESCRIPTION



The FMan interface to support IEEE 1588





PROPERTIES



- compatible

		Usage: required

		Value type: <stringlist>

		Definition: A standard property.

		Must include "fsl,fman-ptp-timer".



- reg

		Usage: required

		Value type: <prop-encoded-array>

		Definition: A standard property.



EXAMPLE



ptp-timer@fe000 {

	compatible = "fsl,fman-ptp-timer";

	reg = <0xfe000 0x1000>;

};



=============================================================================

Example



fman@400000 {

	#address-cells = <1>;

	#size-cells = <1>;

	cell-index = <1>;

	compatible = "fsl,fman"

	ranges = <0 0x400000 0x100000>;

	reg = <0x400000 0x100000>;

	clocks = <&fman_clk>;

	clock-names = "fmanclk";

	interrupts = <

		96 2 0 0

		16 2 1 1>;

	fsl,qman-channel-range = <0x40 0xc>;



	muram@0 {

		compatible = "fsl,fman-muram";

		reg = <0x0 0x28000>;

	};



	port@81000 {

		cell-index = <1>;

		compatible = "fsl,fman-v2-port-oh";

		reg = <0x81000 0x1000>;

	};



	port@82000 {

		cell-index = <2>;

		compatible = "fsl,fman-v2-port-oh";

		reg = <0x82000 0x1000>;

	};



	port@83000 {

		cell-index = <3>;

		compatible = "fsl,fman-v2-port-oh";

		reg = <0x83000 0x1000>;

	};



	port@84000 {

		cell-index = <4>;

		compatible = "fsl,fman-v2-port-oh";

		reg = <0x84000 0x1000>;

	};



	port@85000 {

		cell-index = <5>;

		compatible = "fsl,fman-v2-port-oh";

		reg = <0x85000 0x1000>;

	};



	port@86000 {

		cell-index = <6>;

		compatible = "fsl,fman-v2-port-oh";

		reg = <0x86000 0x1000>;

	};



	fman1_rx_0x8: port@88000 {

		cell-index = <0x8>;

		compatible = "fsl,fman-v2-port-rx";

		reg = <0x88000 0x1000>;

	};



	fman1_rx_0x9: port@89000 {

		cell-index = <0x9>;

		compatible = "fsl,fman-v2-port-rx";

		reg = <0x89000 0x1000>;

	};



	fman1_rx_0xa: port@8a000 {

		cell-index = <0xa>;

		compatible = "fsl,fman-v2-port-rx";

		reg = <0x8a000 0x1000>;

	};



	fman1_rx_0xb: port@8b000 {

		cell-index = <0xb>;

		compatible = "fsl,fman-v2-port-rx";

		reg = <0x8b000 0x1000>;

	};



	fman1_rx_0xc: port@8c000 {

		cell-index = <0xc>;

		compatible = "fsl,fman-v2-port-rx";

		reg = <0x8c000 0x1000>;

	};



	fman1_rx_0x10: port@90000 {

		cell-index = <0x10>;

		compatible = "fsl,fman-v2-port-rx";

		reg = <0x90000 0x1000>;

	};



	fman1_tx_0x28: port@a8000 {

		cell-index = <0x28>;

		compatible = "fsl,fman-v2-port-tx";

		reg = <0xa8000 0x1000>;

	};



	fman1_tx_0x29: port@a9000 {

		cell-index = <0x29>;

		compatible = "fsl,fman-v2-port-tx";

		reg = <0xa9000 0x1000>;

	};



	fman1_tx_0x2a: port@aa000 {

		cell-index = <0x2a>;

		compatible = "fsl,fman-v2-port-tx";

		reg = <0xaa000 0x1000>;

	};



	fman1_tx_0x2b: port@ab000 {

		cell-index = <0x2b>;

		compatible = "fsl,fman-v2-port-tx";

		reg = <0xab000 0x1000>;

	};



	fman1_tx_0x2c: port@ac0000 {

		cell-index = <0x2c>;

		compatible = "fsl,fman-v2-port-tx";

		reg = <0xac000 0x1000>;

	};



	fman1_tx_0x30: port@b0000 {

		cell-index = <0x30>;

		compatible = "fsl,fman-v2-port-tx";

		reg = <0xb0000 0x1000>;

	};



	ethernet@e0000 {

		compatible = "fsl,fman-dtsec";

		cell-index = <0>;

		reg = <0xe0000 0x1000>;

		fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;

	};



	ethernet@e2000 {

		compatible = "fsl,fman-dtsec";

		cell-index = <1>;

		reg = <0xe2000 0x1000>;

		fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>;

	};



	ethernet@e4000 {

		compatible = "fsl,fman-dtsec";

		cell-index = <2>;

		reg = <0xe4000 0x1000>;

		fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>;

	};



	ethernet@e6000 {

		compatible = "fsl,fman-dtsec";

		cell-index = <3>;

		reg = <0xe6000 0x1000>;

		fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>;

	};



	ethernet@e8000 {

		compatible = "fsl,fman-dtsec";

		cell-index = <4>;

		reg = <0xf0000 0x1000>;

		fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>;



	ethernet@f0000 {

		cell-index = <8>;

		compatible = "fsl,fman-xgec";

		reg = <0xf0000 0x1000>;

		fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;

	};



	ptp-timer@fe000 {

		compatible = "fsl,fman-ptp-timer";

		reg = <0xfe000 0x1000>;

	};

};

Documentation/devicetree/bindings/soc/fsl/bman-portals.txt

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QorIQ DPAA Buffer Manager Portals Device Tree Binding



Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.



CONTENTS



	- BMan Portal

	- Example



BMan Portal Node



Portals are memory mapped interfaces to BMan that allow low-latency, lock-less

interaction by software running on processor cores, accelerators and network

interfaces with the BMan



PROPERTIES



- compatible

	Usage:		Required

	Value type:	<stringlist>

	Definition:	Must include "fsl,bman-portal-<hardware revision>"

			May include "fsl,<SoC>-bman-portal" or "fsl,bman-portal"



- reg

	Usage:		Required

	Value type:	<prop-encoded-array>

	Definition:	Two regions. The first is the cache-enabled region of

			the portal. The second is the cache-inhibited region of

			the portal



- interrupts

	Usage:		Required

	Value type:	<prop-encoded-array>

	Definition:	Standard property



EXAMPLE



The example below shows a (P4080) BMan portals container/bus node with two portals



	bman-portals@ff4000000 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "simple-bus";

		ranges = <0 0xf 0xf4000000 0x200000>;



		bman-portal@0 {

			compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";

			reg = <0x0 0x4000>, <0x100000 0x1000>;

			interrupts = <105 2 0 0>;

		};

		bman-portal@4000 {

			compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";

			reg = <0x4000 0x4000>, <0x101000 0x1000>;

			interrupts = <107 2 0 0>;

		};

	};

Documentation/devicetree/bindings/soc/fsl/bman.txt

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QorIQ DPAA Buffer Manager Device Tree Bindings



Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.



CONTENTS



	- BMan Node

	- BMan Private Memory Node

	- Example



BMan Node



The Buffer Manager is part of the Data-Path Acceleration Architecture (DPAA).

BMan supports hardware allocation and deallocation of buffers belonging to pools

originally created by software with configurable depletion thresholds. This

binding covers the CCSR space programming model



PROPERTIES



- compatible

	Usage:		Required

	Value type:	<stringlist>

	Definition:	Must include "fsl,bman"

			May include "fsl,<SoC>-bman"



- reg

	Usage:		Required

	Value type:	<prop-encoded-array>

	Definition:	Registers region within the CCSR address space



The BMan revision information is located in the BMAN_IP_REV_1/2 registers which

are located at offsets 0xbf8 and 0xbfc



- interrupts

	Usage:		Required

	Value type:	<prop-encoded-array>

	Definition:	Standard property. The error interrupt



- fsl,liodn

	Usage:		See pamu.txt

	Value type:	<prop-encoded-array>

	Definition:	PAMU property used for static LIODN assignment



- fsl,iommu-parent

	Usage:		See pamu.txt

	Value type:	<phandle>

	Definition:	PAMU property used for dynamic LIODN assignment



	For additional details about the PAMU/LIODN binding(s) see pamu.txt



Devices connected to a BMan instance via Direct Connect Portals (DCP) must link

to the respective BMan instance



- fsl,bman

	Usage:		Required

	Value type:	<prop-encoded-array>

	Description:	List of phandle and DCP index pairs, to the BMan instance

			to which this device is connected via the DCP



BMan Private Memory Node



BMan requires a contiguous range of physical memory used for the backing store

for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as a

node under the /reserved-memory node



The BMan FBPR memory node must be named "bman-fbpr"



PROPERTIES



- compatible

	Usage:		required

	Value type:	<stringlist>

	Definition:	Must inclide "fsl,bman-fbpr"



The following constraints are relevant to the FBPR private memory:

	- The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to

	  16 GiB

	- The alignment must be a muliptle of the memory size



The size of the FBPR must be chosen by observing the hardware features configured

via the Reset Configuration Word (RCW) and that are relevant to a specific board

(e.g. number of MAC(s) pinned-out, number of offline/host command FMan ports,

etc.). The size configured in the DT must reflect the hardware capabilities and

not the specific needs of an application



For additional details about reserved memory regions see reserved-memory.txt



EXAMPLE



The example below shows a BMan FBPR dynamic allocation memory node



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		bman_fbpr: bman-fbpr {

			compatible = "fsl,bman-fbpr";

			alloc-ranges = <0 0 0xf 0xffffffff>;

			size = <0 0x1000000>;

			alignment = <0 0x1000000>;

		};

	};



The example below shows a (P4080) BMan CCSR-space node



	crypto@300000 {

		...

		fsl,bman = <&bman, 2>;

		...

	};



	bman: bman@31a000 {

		compatible = "fsl,bman";

		reg = <0x31a000 0x1000>;

		interrupts = <16 2 1 2>;

		fsl,liodn = <0x17>;

		memory-region = <&bman_fbpr>;

	};



	fman@400000 {

		...

		fsl,bman = <&bman, 0>;

		...

	};

Documentation/devicetree/bindings/soc/fsl/qman-portals.txt

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QorIQ DPAA Queue Manager Portals Device Tree Binding



Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.



CONTENTS



	- QMan Portal

	- QMan Pool Channel

	- Example



QMan Portal Node



Portals are memory mapped interfaces to QMan that allow low-latency, lock-less

interaction by software running on processor cores, accelerators and network

interfaces with the QMan



PROPERTIES



- compatible

	Usage:		Required

	Value type:	<stringlist>

	Definition:	Must include "fsl,qman-portal-<hardware revision>"

			May include "fsl,<SoC>-qman-portal" or "fsl,qman-portal"



- reg

	Usage:		Required

	Value type:	<prop-encoded-array>

	Definition:	Two regions. The first is the cache-enabled region of

			the portal. The second is the cache-inhibited region of

			the portal



- interrupts

	Usage:		Required

	Value type:	<prop-encoded-array>

	Definition:	Standard property



- fsl,liodn

	Usage:		See pamu.txt

	Value type:	<prop-encoded-array>

	Definition:	Two LIODN(s). DQRR LIODN (DLIODN) and Frame LIODN

			(FLIODN)



- fsl,iommu-parent

	Usage:		See pamu.txt

	Value type:	<phandle>

	Definition:	PAMU property used for dynamic LIODN assignment



	For additional details about the PAMU/LIODN binding(s) see pamu.txt



- fsl,qman-channel-id

	Usage:		Required

	Value type:	<u32>

	Definition:	The hardware index of the channel. This can also be

			determined by dividing any of the channel's 8 work queue

			IDs by 8



In addition to these properties the qman-portals should have sub-nodes to

represent the HW devices/portals that are connected to the software portal

described here



The currently supported sub-nodes are:

	* fman0

	* fman1

	* pme

	* crypto



These subnodes should have the following properties:



- fsl,liodn

	Usage:		See pamu.txt

	Value type:	<prop-encoded-array>

	Definition:	PAMU property used for static LIODN assignment



- fsl,iommu-parent

	Usage:		See pamu.txt

	Value type:	<phandle>

	Definition:	PAMU property used for dynamic LIODN assignment



- dev-handle

	Usage:		Required

	Value type:	<phandle>

	Definition:	The phandle to the particular hardware device that this

			portal is connected to.



DPAA QMan Pool Channel Nodes



Pool Channels are defined with the following properties.



PROPERTIES



- compatible

	Usage:		Required

	Value type:	<stringlist>

	Definition:	Must include "fsl,qman-pool-channel"

			May include "fsl,<SoC>-qman-pool-channel"



- fsl,qman-channel-id

	Usage:		Required

	Value type:	<u32>

	Definition:	The hardware index of the channel. This can also be

			determined by dividing any of the channel's 8 work queue

			IDs by 8



EXAMPLE



The example below shows a (P4080) QMan portals container/bus node with two portals



	qman-portals@ff4200000 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "simple-bus";

		ranges = <0 0xf 0xf4200000 0x200000>;



		qman-portal@0 {

			compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";

			reg = <0 0x4000>, <0x100000 0x1000>;

			interrupts = <104 2 0 0>;

			fsl,liodn = <1 2>;

			fsl,qman-channel-id = <0>;



			fman0 {

				fsl,liodn = <0x21>;

				dev-handle = <&fman0>;

			};

			fman1 {

				fsl,liodn = <0xa1>;

				dev-handle = <&fman1>;

			};

			crypto {

				fsl,liodn = <0x41 0x66>;

				dev-handle = <&crypto>;

			};

		};

		qman-portal@4000 {

			compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";

			reg = <0x4000 0x4000>, <0x101000 0x1000>;

			interrupts = <106 2 0 0>;

			fsl,liodn = <3 4>;

			fsl,qman-channel-id = <1>;



			fman0 {

				fsl,liodn = <0x22>;

				dev-handle = <&fman0>;

			};

			fman1 {

				fsl,liodn = <0xa2>;

				dev-handle = <&fman1>;

			};

			crypto {

				fsl,liodn = <0x42 0x67>;

				dev-handle = <&crypto>;

			};

		};

	};

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