Commit 3551ff92 authored by José Roberto de Souza's avatar José Roberto de Souza
Browse files

drm/i915/gen11: Moving WAs to rcs_engine_wa_init() 



This are register of render engine, so after a render reset those
would return to the default value and init_clock_gating() is not
called for single engine reset.
So here moving it rcs_engine_wa_init() that will guarantee that this
WAs will not be lost.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200302231421.224322-1-jose.souza@intel.com
parent 9b234d26

drivers/gpu/drm/i915/gt/intel_workarounds.c

+15 −0
Original line number Diff line number Diff line
@@ -1454,6 +1454,21 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
				   GEN11_SCRATCH2,

				   GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,

				   0);



		/* WaEnable32PlaneMode:icl */

		wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS,

			     GEN11_ENABLE_32_PLANE_MODE);



		/*

		 * Wa_1408615072:icl,ehl  (vsunit)

		 * Wa_1407596294:icl,ehl  (hsunit)

		 */

		wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE,

			     VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);



		/* Wa_1407352427:icl,ehl */

		wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,

			     PSDUNIT_CLKGATE_DIS);

	}



	if (IS_GEN_RANGE(i915, 9, 11)) {

drivers/gpu/drm/i915/intel_pm.c

+0 −15
Original line number Diff line number Diff line
@@ -6806,21 +6806,6 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv) 
	I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,

		   I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);



	/* WaEnable32PlaneMode:icl */

	I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,

		   _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));



	/*

	 * Wa_1408615072:icl,ehl  (vsunit)

	 * Wa_1407596294:icl,ehl  (hsunit)

	 */

	intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE,

			 0, VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);



	/* Wa_1407352427:icl,ehl */

	intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2,

			 0, PSDUNIT_CLKGATE_DIS);



	/*Wa_14010594013:icl, ehl */

	intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,

			 0, CNL_DELAY_PMRSP);

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