Merge branches 'pci/host-designware', 'pci/host-dra7xx', 'pci/host-exynos',...

Freescale Layerscape PCIe controller

This PCIe host controller is based on the Synopsis Designware PCIe IP

and thus inherits all the common properties defined in designware-pcie.txt.

Required properties:

- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie"

- reg: base addresses and lengths of the PCIe controller

- interrupts: A list of interrupt outputs of the controller. Must contain an

  entry for each entry in the interrupt-names property.

- interrupt-names: Must include the following entries:

  "intr": The interrupt that is asserted for controller interrupts

- fsl,pcie-scfg: Must include two entries.

  The first entry must be a link to the SCFG device node

  The second entry must be '0' or '1' based on physical PCIe controller index.

  This is used to get SCFG PEXN registers

Example:

	pcie@3400000 {

		compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";

		reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */

		       0x40 0x00000000 0x0 0x00002000>; /* configuration space */

		reg-names = "regs", "config";

		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */

		interrupt-names = "intr";

		fsl,pcie-scfg = <&scfg 0>;

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		num-lanes = <4>;

		bus-range = <0x0 0xff>;

		ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */

			  0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000   /* prefetchable memory */

			  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,

				<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,

				<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,

				<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;

	};

F:	Documentation/devicetree/bindings/pci/xgene-pci.txt

F:	drivers/pci/host/pci-xgene.c

PCI DRIVER FOR FREESCALE LAYERSCAPE

M:	Minghuan Lian <minghuan.Lian@freescale.com>

M:	Mingkai Hu <mingkai.hu@freescale.com>

M:	Roy Zang <tie-fei.zang@freescale.com>

L:	linuxppc-dev@lists.ozlabs.org

L:	linux-pci@vger.kernel.org

L:	linux-arm-kernel@lists.infradead.org

S:	Maintained

F:	drivers/pci/host/*layerscape*

PCI DRIVER FOR IMX6

M:	Richard Zhu <r65037@freescale.com>

M:	Lucas Stach <l.stach@pengutronix.de>

config PCI_TEGRA

	bool "NVIDIA Tegra PCIe controller"

	depends on ARCH_TEGRA

	depends on ARCH_TEGRA && !ARM64

	help

	  Say Y here if you want support for the PCIe host controller found

	  on NVIDIA Tegra SoCs.

config PCI_RCAR_GEN2

	bool "Renesas R-Car Gen2 Internal PCI controller"

	  There are 5 internal PCIe ports available. Each port is GEN3 capable

	  and have varied lanes from x1 to x8.

config PCI_LAYERSCAPE

	bool "Freescale Layerscape PCIe controller"

	depends on OF && ARM

	select PCIE_DW

	select MFD_SYSCON

	help

	  Say Y here if you want PCIe controller support on Layerscape SoCs.

endmenu

obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o

obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o

obj-$(CONFIG_PCI_XGENE) += pci-xgene.o

obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o

	return IRQ_HANDLED;

}

static int add_pcie_port(struct dra7xx_pcie *dra7xx,

static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,

				       struct platform_device *pdev)

{

	int ret;

	platform_set_drvdata(pdev, dra7xx);

	ret = add_pcie_port(dra7xx, pdev);

	ret = dra7xx_add_pcie_port(dra7xx, pdev);

	if (ret < 0)

		goto err_add_port;