MIPS: fw: arc: workaround 64bit kernel/32bit ARC problems

#include <asm/bcache.h>

#include <asm/setup.h>

#if defined(CONFIG_64BIT) && defined(CONFIG_FW_ARC32)

/*

 * For 64bit kernels working with a 32bit ARC PROM pointer arguments

 * for ARC calls need to reside in CKEG0/1. But as soon as the kernel

 * switches to it's first kernel thread stack is set to an address in

 * XKPHYS, so anything on stack can't be used anymore. This is solved

 * by using a * static declartion variables are put into BSS, which is

 * linked to a CKSEG0 address. Since this is only used on UP platforms

 * there is not spinlock needed

 */

#define O32_STATIC	static

#else

#define O32_STATIC

#endif

/*

 * IP22 boardcache is not compatible with board caches.	 Thus we disable it

 * during romvec action.  Since r4xx0.c is always compiled and linked with your

void prom_putchar(char c)

{

	ULONG cnt;

	CHAR it = c;

	O32_STATIC ULONG cnt;

	O32_STATIC CHAR it;

	it = c;

	bc_disable();

	ArcWrite(1, &it, 1, &cnt);

char prom_getchar(void)

{

	ULONG cnt;

	CHAR c;

	O32_STATIC ULONG cnt;

	O32_STATIC CHAR c;

	bc_disable();

	ArcRead(0, &c, 1, &cnt);