Commit 34edea7a authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge branch 'tegra/dma-reset-rework' into next/soc 



Bringing in the tegra dma/reset rework as a base for new SoC branches.

* tegra/dma-reset-rework: (81 commits)
  spi: tegra: checking for ERR_PTR instead of NULL
  ASoC: tegra: update module reset list for Tegra124
  clk: tegra: remove bogus PCIE_XCLK
  clk: tegra: remove legacy reset APIs
  ARM: tegra: remove legacy DMA entries from DT
  ARM: tegra: remove legacy clock entries from DT
  USB: EHCI: tegra: use reset framework
  Input: tegra-kbc - use reset framework
  serial: tegra: convert to standard DMA DT bindings
  serial: tegra: use reset framework
  spi: tegra: convert to standard DMA DT bindings
  spi: tegra: use reset framework
  staging: nvec: use reset framework
  i2c: tegra: use reset framework
  ASoC: tegra: convert to standard DMA DT bindings
  ASoC: tegra: allocate AHUB FIFO during probe() not startup()
  ASoC: tegra: call pm_runtime APIs around register accesses
  ASoC: tegra: use reset framework
  dma: tegra: register as an OF DMA controller
  dma: tegra: use reset framework
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 9b20d1c9 8a0a1af3

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt

+1 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ Required properties: 
- compatible : Should contain "nvidia,tegra<chip>-pmc".

- reg : Offset and length of the register set for the device

- clocks : Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names : Must include the following entries:

  "pclk" (The Tegra clock of that name),

  "clk32k_in" (The 32KHz clock input to Tegra).

Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt

+4 −0
Original line number Diff line number Diff line
@@ -15,6 +15,9 @@ Required properties : 
  In clock consumers, this cell represents the clock ID exposed by the

  CAR. The assignments may be found in header file

  <dt-bindings/clock/tegra114-car.h>.

- #reset-cells : Should be 1.

  In clock consumers, this cell represents the bit number in the CAR's

  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.



Example SoC include file:
@@ -23,6 +26,7 @@ Example SoC include file: 
		compatible = "nvidia,tegra114-car";

		reg = <0x60006000 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	usb@c5004000 {

Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt

0 → 100644
+63 −0
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NVIDIA Tegra124 Clock And Reset Controller



This binding uses the common clock binding:

Documentation/devicetree/bindings/clock/clock-bindings.txt



The CAR (Clock And Reset) Controller on Tegra is the HW module responsible

for muxing and gating Tegra's clocks, and setting their rates.



Required properties :

- compatible : Should be "nvidia,tegra124-car"

- reg : Should contain CAR registers location and length

- clocks : Should contain phandle and clock specifiers for two clocks:

  the 32 KHz "32k_in", and the board-specific oscillator "osc".

- #clock-cells : Should be 1.

  In clock consumers, this cell represents the clock ID exposed by the

  CAR. The assignments may be found in header file

  <dt-bindings/clock/tegra124-car.h>.

- #reset-cells : Should be 1.

  In clock consumers, this cell represents the bit number in the CAR's

  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.



Example SoC include file:



/ {

	tegra_car: clock {

		compatible = "nvidia,tegra124-car";

		reg = <0x60006000 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	usb@c5004000 {

		clocks = <&tegra_car TEGRA124_CLK_USB2>;

	};

};



Example board file:



/ {

	clocks {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <0>;



		osc: clock@0 {

			compatible = "fixed-clock";

			reg = <0>;

			#clock-cells = <0>;

			clock-frequency = <112400000>;

		};



		clk_32k: clock@1 {

			compatible = "fixed-clock";

			reg = <1>;

			#clock-cells = <0>;

			clock-frequency = <32768>;

		};

	};



	&tegra_car {

		clocks = <&clk_32k> <&osc>;

	};

};

Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt

+4 −0
Original line number Diff line number Diff line
@@ -15,6 +15,9 @@ Required properties : 
  In clock consumers, this cell represents the clock ID exposed by the

  CAR. The assignments may be found in header file

  <dt-bindings/clock/tegra20-car.h>.

- #reset-cells : Should be 1.

  In clock consumers, this cell represents the bit number in the CAR's

  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.



Example SoC include file:
@@ -23,6 +26,7 @@ Example SoC include file: 
		compatible = "nvidia,tegra20-car";

		reg = <0x60006000 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	usb@c5004000 {

Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt

+4 −0
Original line number Diff line number Diff line
@@ -15,6 +15,9 @@ Required properties : 
  In clock consumers, this cell represents the clock ID exposed by the

  CAR. The assignments may be found in header file

  <dt-bindings/clock/tegra30-car.h>.

- #reset-cells : Should be 1.

  In clock consumers, this cell represents the bit number in the CAR's

  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.



Example SoC include file:
@@ -23,6 +26,7 @@ Example SoC include file: 
		compatible = "nvidia,tegra30-car";

		reg = <0x60006000 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	usb@c5004000 {

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