Commit 34d903d1 authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amd/pm: update driver if file for sienna cichlid 



Update driver if file for sienna cichlid.

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 93a80241

drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h

+11 −5
Original line number Diff line number Diff line
@@ -27,9 +27,9 @@ 
// *** IMPORTANT ***

// SMU TEAM: Always increment the interface version if 

// any structure is changed in this file

#define SMU11_DRIVER_IF_VERSION 0x3A

#define SMU11_DRIVER_IF_VERSION 0x3B



#define PPTABLE_Sienna_Cichlid_SMU_VERSION 6

#define PPTABLE_Sienna_Cichlid_SMU_VERSION 7



#define NUM_GFXCLK_DPM_LEVELS  16

#define NUM_SMNCLK_DPM_LEVELS  2
@@ -437,6 +437,7 @@ typedef enum { 
  PIECEWISE_LINEAR_FUSED_MODEL = 0,

  PIECEWISE_LINEAR_PP_MODEL,

  QUADRATIC_PP_MODEL,

  PERPART_PIECEWISE_LINEAR_PP_MODEL,  

} DfllDroopModelSelect_e;



typedef struct {
@@ -612,7 +613,9 @@ typedef struct { 
  uint16_t       SmnclkDpmFreq        [NUM_SMNCLK_DPM_LEVELS];       // in MHz

  uint16_t       SmnclkDpmVoltage     [NUM_SMNCLK_DPM_LEVELS];       // mV(Q2)



  uint32_t     PaddingAPCC[4];

  uint32_t       PaddingAPCC;

  uint16_t       PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS];  //In mV(Q2)

  uint16_t       PaddingPerPartDroop;



  // SECTION: Throttler settings

  uint32_t ThrottlerControlMask;   // See Throtter masks defines
@@ -667,7 +670,9 @@ typedef struct { 
  uint16_t       FreqTablePhyclk   [NUM_PHYCLK_DPM_LEVELS  ];     // In MHz

  uint16_t       FreqTableDtbclk   [NUM_DTBCLK_DPM_LEVELS  ];     // In MHz

  uint16_t       FreqTableFclk     [NUM_FCLK_DPM_LEVELS    ];     // In MHz

  uint32_t       Paddingclks[16];

  uint32_t       Paddingclks;



  DroopInt_t     PerPartDroopModelGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //GHz ->Vstore in IEEE float format



  uint32_t       DcModeMaxFreq     [PPCLK_COUNT            ];     // In MHz
@@ -1221,7 +1226,8 @@ typedef struct { 
#define WORKLOAD_PPLIB_VR_BIT             4 

#define WORKLOAD_PPLIB_COMPUTE_BIT        5 

#define WORKLOAD_PPLIB_CUSTOM_BIT         6 

#define WORKLOAD_PPLIB_COUNT              7 

#define WORKLOAD_PPLIB_W3D_BIT            7 

#define WORKLOAD_PPLIB_COUNT              8 





// These defines are used with the following messages:

drivers/gpu/drm/amd/pm/inc/smu_v11_0.h

+1 −1
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ 
#define SMU11_DRIVER_IF_VERSION_NV10 0x36

#define SMU11_DRIVER_IF_VERSION_NV12 0x36

#define SMU11_DRIVER_IF_VERSION_NV14 0x36

#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3A

#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3B

#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5

#define SMU11_DRIVER_IF_VERSION_VANGOGH 0x02

#define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xD

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

+0 −22
Original line number Diff line number Diff line
@@ -1805,11 +1805,6 @@ static void sienna_cichlid_dump_pptable(struct smu_context *smu) 
		dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);

		dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);

	}

	dev_info(smu->adev->dev, "PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]);

	dev_info(smu->adev->dev, "PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]);

	dev_info(smu->adev->dev, "PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]);

	dev_info(smu->adev->dev, "PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]);



	dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);



	dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
@@ -2036,23 +2031,6 @@ static void sienna_cichlid_dump_pptable(struct smu_context *smu) 
	for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)

		dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);



	dev_info(smu->adev->dev, "Paddingclks[0] = 0x%x\n",  pptable->Paddingclks[0]);

	dev_info(smu->adev->dev, "Paddingclks[1] = 0x%x\n",  pptable->Paddingclks[1]);

	dev_info(smu->adev->dev, "Paddingclks[2] = 0x%x\n",  pptable->Paddingclks[2]);

	dev_info(smu->adev->dev, "Paddingclks[3] = 0x%x\n",  pptable->Paddingclks[3]);

	dev_info(smu->adev->dev, "Paddingclks[4] = 0x%x\n",  pptable->Paddingclks[4]);

	dev_info(smu->adev->dev, "Paddingclks[5] = 0x%x\n",  pptable->Paddingclks[5]);

	dev_info(smu->adev->dev, "Paddingclks[6] = 0x%x\n",  pptable->Paddingclks[6]);

	dev_info(smu->adev->dev, "Paddingclks[7] = 0x%x\n",  pptable->Paddingclks[7]);

	dev_info(smu->adev->dev, "Paddingclks[8] = 0x%x\n",  pptable->Paddingclks[8]);

	dev_info(smu->adev->dev, "Paddingclks[9] = 0x%x\n",  pptable->Paddingclks[9]);

	dev_info(smu->adev->dev, "Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]);

	dev_info(smu->adev->dev, "Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]);

	dev_info(smu->adev->dev, "Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]);

	dev_info(smu->adev->dev, "Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]);

	dev_info(smu->adev->dev, "Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]);

	dev_info(smu->adev->dev, "Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]);



	dev_info(smu->adev->dev, "DcModeMaxFreq\n");

	dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);

	dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);

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