Commit 34c0f6f2 authored by Maciej S. Szmigiero's avatar Maciej S. Szmigiero Committed by Paolo Bonzini
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KVM: mmu: Fix SPTE encoding of MMIO generation upper half 



Commit cae7ed3c ("KVM: x86: Refactor the MMIO SPTE generation handling")
cleaned up the computation of MMIO generation SPTE masks, however it
introduced a bug how the upper part was encoded:
SPTE bits 52-61 were supposed to contain bits 10-19 of the current
generation number, however a missing shift encoded bits 1-10 there instead
(mostly duplicating the lower part of the encoded generation number that
then consisted of bits 1-9).

In the meantime, the upper part was shrunk by one bit and moved by
subsequent commits to become an upper half of the encoded generation number
(bits 9-17 of bits 0-17 encoded in a SPTE).

In addition to the above, commit 56871d44 ("KVM: x86: fix overlap between SPTE_MMIO_MASK and generation")
has changed the SPTE bit range assigned to encode the generation number and
the total number of bits encoded but did not update them in the comment
attached to their defines, nor in the KVM MMU doc.
Let's do it here, too, since it is too trivial thing to warrant a separate
commit.

Fixes: cae7ed3c ("KVM: x86: Refactor the MMIO SPTE generation handling")
Signed-off-by: default avatarMaciej S. Szmigiero <maciej.szmigiero@oracle.com>
Message-Id: <156700708db2a5296c5ed7a8b9ac71f1e9765c85.1607129096.git.maciej.szmigiero@oracle.com>
Cc: stable@vger.kernel.org
[Reorganize macros so that everything is computed from the bit ranges. - Paolo]
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 83bbb8ff

Documentation/virt/kvm/mmu.rst

+1 −1
Original line number Diff line number Diff line
@@ -455,7 +455,7 @@ If the generation number of the spte does not equal the global generation 
number, it will ignore the cached MMIO information and handle the page

fault through the slow path.



Since only 19 bits are used to store generation-number on mmio spte, all

Since only 18 bits are used to store generation-number on mmio spte, all

pages are zapped when there is an overflow.



Unfortunately, a single memory access might access kvm_memslots(kvm) multiple

arch/x86/kvm/mmu/spte.c

+2 −2
Original line number Diff line number Diff line
@@ -40,8 +40,8 @@ static u64 generation_mmio_spte_mask(u64 gen) 
	WARN_ON(gen & ~MMIO_SPTE_GEN_MASK);

	BUILD_BUG_ON((MMIO_SPTE_GEN_HIGH_MASK | MMIO_SPTE_GEN_LOW_MASK) & SPTE_SPECIAL_MASK);



	mask = (gen << MMIO_SPTE_GEN_LOW_START) & MMIO_SPTE_GEN_LOW_MASK;

	mask |= (gen << MMIO_SPTE_GEN_HIGH_START) & MMIO_SPTE_GEN_HIGH_MASK;

	mask = (gen << MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_SPTE_GEN_LOW_MASK;

	mask |= (gen << MMIO_SPTE_GEN_HIGH_SHIFT) & MMIO_SPTE_GEN_HIGH_MASK;

	return mask;

}

arch/x86/kvm/mmu/spte.h

+18 −7
Original line number Diff line number Diff line
@@ -56,11 +56,11 @@ 
#define SPTE_MMU_WRITEABLE	(1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))



/*

 * Due to limited space in PTEs, the MMIO generation is a 19 bit subset of

 * Due to limited space in PTEs, the MMIO generation is a 18 bit subset of

 * the memslots generation and is derived as follows:

 *

 * Bits 0-8 of the MMIO generation are propagated to spte bits 3-11

 * Bits 9-18 of the MMIO generation are propagated to spte bits 52-61

 * Bits 9-17 of the MMIO generation are propagated to spte bits 54-62

 *

 * The KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS flag is intentionally not included in

 * the MMIO generation number, as doing so would require stealing a bit from
@@ -69,18 +69,29 @@ 
 * requires a full MMU zap).  The flag is instead explicitly queried when

 * checking for MMIO spte cache hits.

 */

#define MMIO_SPTE_GEN_MASK		GENMASK_ULL(17, 0)



#define MMIO_SPTE_GEN_LOW_START		3

#define MMIO_SPTE_GEN_LOW_END		11

#define MMIO_SPTE_GEN_LOW_MASK		GENMASK_ULL(MMIO_SPTE_GEN_LOW_END, \

						    MMIO_SPTE_GEN_LOW_START)



#define MMIO_SPTE_GEN_HIGH_START	PT64_SECOND_AVAIL_BITS_SHIFT

#define MMIO_SPTE_GEN_HIGH_END		62



#define MMIO_SPTE_GEN_LOW_MASK		GENMASK_ULL(MMIO_SPTE_GEN_LOW_END, \

						    MMIO_SPTE_GEN_LOW_START)

#define MMIO_SPTE_GEN_HIGH_MASK		GENMASK_ULL(MMIO_SPTE_GEN_HIGH_END, \

						    MMIO_SPTE_GEN_HIGH_START)



#define MMIO_SPTE_GEN_LOW_BITS		(MMIO_SPTE_GEN_LOW_END - MMIO_SPTE_GEN_LOW_START + 1)

#define MMIO_SPTE_GEN_HIGH_BITS		(MMIO_SPTE_GEN_HIGH_END - MMIO_SPTE_GEN_HIGH_START + 1)



/* remember to adjust the comment above as well if you change these */

static_assert(MMIO_SPTE_GEN_LOW_BITS == 9 && MMIO_SPTE_GEN_HIGH_BITS == 9);



#define MMIO_SPTE_GEN_LOW_SHIFT		(MMIO_SPTE_GEN_LOW_START - 0)

#define MMIO_SPTE_GEN_HIGH_SHIFT	(MMIO_SPTE_GEN_HIGH_START - MMIO_SPTE_GEN_LOW_BITS)



#define MMIO_SPTE_GEN_MASK		GENMASK_ULL(MMIO_SPTE_GEN_LOW_BITS + MMIO_SPTE_GEN_HIGH_BITS - 1, 0)



extern u64 __read_mostly shadow_nx_mask;

extern u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */

extern u64 __read_mostly shadow_user_mask;
@@ -228,8 +239,8 @@ static inline u64 get_mmio_spte_generation(u64 spte) 
{

	u64 gen;



	gen = (spte & MMIO_SPTE_GEN_LOW_MASK) >> MMIO_SPTE_GEN_LOW_START;

	gen |= (spte & MMIO_SPTE_GEN_HIGH_MASK) >> MMIO_SPTE_GEN_HIGH_START;

	gen = (spte & MMIO_SPTE_GEN_LOW_MASK) >> MMIO_SPTE_GEN_LOW_SHIFT;

	gen |= (spte & MMIO_SPTE_GEN_HIGH_MASK) >> MMIO_SPTE_GEN_HIGH_SHIFT;

	return gen;

}

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