Commit 34ab0316 authored by Christoph Hellwig's avatar Christoph Hellwig
Browse files

arm-nommu: remove the partial DMA_ATTR_NON_CONSISTENT support 



The arm-nommu DMA code supports DMA_ATTR_NON_CONSISTENT allocations, but
does not provide a cache_sync operation.  This means any user of it
will never be able to actually transfer cache ownership and thus cause
coherency bugs.

Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Reviewed-by: default avatarVladimir Murzin <vladimir.murzin@arm.com>
parent ab746573

arch/arm/mm/dma-mapping-nommu.c

+3 −21
Original line number Diff line number Diff line
@@ -39,18 +39,7 @@ static void *arm_nommu_dma_alloc(struct device *dev, size_t size, 
				 unsigned long attrs)



{

	void *ret;



	/*

	 * Try generic allocator first if we are advertised that

	 * consistency is not required.

	 */



	if (attrs & DMA_ATTR_NON_CONSISTENT)

		return dma_direct_alloc_pages(dev, size, dma_handle, gfp,

				attrs);



	ret = dma_alloc_from_global_coherent(size, dma_handle);

	void *ret = dma_alloc_from_global_coherent(size, dma_handle);



	/*

	 * dma_alloc_from_global_coherent() may fail because:
@@ -70,18 +59,11 @@ static void arm_nommu_dma_free(struct device *dev, size_t size, 
			       void *cpu_addr, dma_addr_t dma_addr,

			       unsigned long attrs)

{

	if (attrs & DMA_ATTR_NON_CONSISTENT) {

		dma_direct_free_pages(dev, size, cpu_addr, dma_addr, attrs);

	} else {

		int ret = dma_release_from_global_coherent(get_order(size),

							   cpu_addr);

	int ret = dma_release_from_global_coherent(get_order(size), cpu_addr);



	WARN_ON_ONCE(ret == 0);

}



	return;

}



static int arm_nommu_dma_mmap(struct device *dev, struct vm_area_struct *vma,

			      void *cpu_addr, dma_addr_t dma_addr, size_t size,

			      unsigned long attrs)

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