drm/amdgpu/gfx8: use cached raster config values in csb setup

	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));

	buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG -

			PACKET3_SET_CONTEXT_REG_START);

	switch (adev->asic_type) {

	case CHIP_TONGA:

	case CHIP_POLARIS10:

		buffer[count++] = cpu_to_le32(0x16000012);

		buffer[count++] = cpu_to_le32(0x0000002A);

		break;

	case CHIP_POLARIS11:

		buffer[count++] = cpu_to_le32(0x16000012);

		buffer[count++] = cpu_to_le32(0x00000000);

		break;

	case CHIP_FIJI:

		buffer[count++] = cpu_to_le32(0x3a00161a);

		buffer[count++] = cpu_to_le32(0x0000002e);

		break;

	case CHIP_TOPAZ:

	case CHIP_CARRIZO:

		buffer[count++] = cpu_to_le32(0x00000002);

		buffer[count++] = cpu_to_le32(0x00000000);

		break;

	case CHIP_STONEY:

		buffer[count++] = cpu_to_le32(0x00000000);

		buffer[count++] = cpu_to_le32(0x00000000);

		break;

	default:

		buffer[count++] = cpu_to_le32(0x00000000);

		buffer[count++] = cpu_to_le32(0x00000000);

		break;

	}

	buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);

	buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1);

	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));

	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);