Commit 345429a6 authored by Harry Wentland's avatar Harry Wentland Committed by Alex Deucher
Browse files

drm/amd/display: Add DCN2 DWB 



Add support to program the DCN2 DWB (Display Writeback)

HW Blocks:

 +--------++------+       +----------+
 | HUBBUB || HUBP |  <--  | MMHUBBUB |
 +--------++------+       +----------+
        |                     ^
        v                     |
    +--------+            +--------+
    |  DPP   |            |  DWB   |
    +--------+            +--------+
        |
        v                      ^
    +--------+                 |
    |  MPC   |                 |
    +--------+                 |
        |                      |
        v                      |
    +-------+                  |
    |  OPP  |                  |
    +-------+                  |
        |                      |
        v                      |
    +--------+                /
    |  OPTC  |  --------------
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fa0d2c98

drivers/gpu/drm/amd/display/dc/dc_types.h

+26 −0
Original line number Diff line number Diff line
@@ -421,6 +421,32 @@ enum display_content_type { 
	DISPLAY_CONTENT_TYPE_GAME = 8

};



#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

/* writeback */

struct dc_dwb_cnv_params {

	unsigned int		src_width;	/* input active width */

	unsigned int		src_height;	/* input active height (half-active height in interlaced mode) */

	unsigned int		crop_width;	/* cropped window width at cnv output */

	bool			crop_en;	/* window cropping enable in cnv */

	unsigned int		crop_height;	/* cropped window height at cnv output */

	unsigned int		crop_x;		/* cropped window start x value at cnv output */

	unsigned int		crop_y;		/* cropped window start y value at cnv output */

	enum dwb_cnv_out_bpc cnv_out_bpc;	/* cnv output pixel depth - 8bpc or 10bpc */

};



struct dc_dwb_params {

	struct dc_dwb_cnv_params	cnv_params;	/* CNV source size and cropping window parameters */

	unsigned int			dest_width;	/* Destination width */

	unsigned int			dest_height;	/* Destination height */

	enum dwb_scaler_mode		out_format;	/* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */

	enum dwb_output_depth		output_depth;	/* output pixel depth - 8bpc or 10bpc */

	enum dwb_capture_rate		capture_rate;	/* controls the frame capture rate */

	struct scaling_taps 		scaler_taps;	/* Scaling taps */

	enum dwb_subsample_position	subsample_position;

	struct dc_transfer_func *out_transfer_func;

};

#endif



/* audio*/



union audio_sample_rates {

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

0 → 100644
+136 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2012-17 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */



#if defined(CONFIG_DRM_AMD_DC_DCN1_0)



#include "reg_helper.h"

#include "resource.h"

#include "dwb.h"

#include "dcn10_dwb.h"





#define REG(reg)\

	dwbc10->dwbc_regs->reg



#define CTX \

	dwbc10->base.ctx



#undef FN

#define FN(reg_name, field_name) \

	dwbc10->dwbc_shift->field_name, dwbc10->dwbc_mask->field_name



#define TO_DCN10_DWBC(dwbc_base) \

	container_of(dwbc_base, struct dcn10_dwbc, base)



static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)

{

	if (caps) {

		caps->adapter_id = 0;	/* we only support 1 adapter currently */

		caps->hw_version = DCN_VERSION_1_0;

		caps->num_pipes = 2;

		memset(&caps->reserved, 0, sizeof(caps->reserved));

		memset(&caps->reserved2, 0, sizeof(caps->reserved2));

		caps->sw_version = dwb_ver_1_0;

		caps->caps.support_dwb = true;

		caps->caps.support_ogam = false;

		caps->caps.support_wbscl = true;

		caps->caps.support_ocsc = false;

		return true;

	} else {

		return false;

	}

}



static bool dwb1_enable(struct dwbc *dwbc, struct dc_dwb_params *params)

{

	struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);



	/* disable first. */

	dwbc->funcs->disable(dwbc);



	/* disable power gating */

	REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 1,

		 DISPCLK_G_WB_GATE_DIS, 1, DISPCLK_G_WBSCL_GATE_DIS, 1,

		 WB_LB_LS_DIS, 1, WB_LUT_LS_DIS, 1);



	REG_UPDATE(WB_ENABLE, WB_ENABLE, 1);



	return true;

}



static bool dwb1_disable(struct dwbc *dwbc)

{

	struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);



	/* disable CNV */

	REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, 0);



	/* disable WB */

	REG_UPDATE(WB_ENABLE, WB_ENABLE, 0);



	/* soft reset */

	REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 1);

	REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 0);



	/* enable power gating */

	REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 0,

		 DISPCLK_G_WB_GATE_DIS, 0, DISPCLK_G_WBSCL_GATE_DIS, 0,

		 WB_LB_LS_DIS, 0, WB_LUT_LS_DIS, 0);



	return true;

}



const struct dwbc_funcs dcn10_dwbc_funcs = {

	.get_caps			= dwb1_get_caps,

	.enable				= dwb1_enable,

	.disable			= dwb1_disable,

	.update				= NULL,

	.set_stereo			= NULL,

	.set_new_content		= NULL,

#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

	.set_warmup			= NULL,

#endif

	.dwb_set_scaler			= NULL,

};



void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,

		struct dc_context *ctx,

		const struct dcn10_dwbc_registers *dwbc_regs,

		const struct dcn10_dwbc_shift *dwbc_shift,

		const struct dcn10_dwbc_mask *dwbc_mask,

		int inst)

{

	dwbc10->base.ctx = ctx;



	dwbc10->base.inst = inst;

	dwbc10->base.funcs = &dcn10_dwbc_funcs;



	dwbc10->dwbc_regs = dwbc_regs;

	dwbc10->dwbc_shift = dwbc_shift;

	dwbc10->dwbc_mask = dwbc_mask;

}





#endif

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

0 → 100644
+271 −0
Original line number Diff line number Diff line 
/* Copyright 2012-17 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */

#ifndef __DC_DWBC_DCN10_H__

#define __DC_DWBC_DCN10_H__



#if defined(CONFIG_DRM_AMD_DC_DCN1_0)



/* DCN */

#define BASE_INNER(seg) \

	DCE_BASE__INST0_SEG ## seg



#define BASE(seg) \

	BASE_INNER(seg)



#define SR(reg_name)\

		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \

					mm ## reg_name



#define SRI(reg_name, block, id)\

	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

					mm ## block ## id ## _ ## reg_name





#define SRII(reg_name, block, id)\

	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

					mm ## block ## id ## _ ## reg_name



#define SF(reg_name, field_name, post_fix)\

	.field_name = reg_name ## __ ## field_name ## post_fix





#define DWBC_COMMON_REG_LIST_DCN1_0(inst) \

	SRI(WB_ENABLE, CNV, inst),\

	SRI(WB_EC_CONFIG, CNV, inst),\

	SRI(CNV_MODE, CNV, inst),\

	SRI(WB_SOFT_RESET, CNV, inst),\

	SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\

	SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\

	SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\

	SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\

	SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\

	SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\

	SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\

	SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\

	SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\

	SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\

	SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\

	SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\

	SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\

	SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\

	SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\

	SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\

	SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\

	SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\

	SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\

	SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\

	SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\

	SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\

	SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\

	SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\

	SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\

	SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\

	SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst)



#define DWBC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh) \

	SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\

	SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\

	SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\

	SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\

	SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\

	SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\

	SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\

	SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\

	SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\

	SF(CNV0_CNV_MODE, CNV_EYE_SELECTION, mask_sh),\

	SF(CNV0_CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\

	SF(CNV0_CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\

	SF(CNV0_CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\

	SF(CNV0_CNV_MODE, CNV_NEW_CONTENT, mask_sh),\

	SF(CNV0_CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\

	SF(CNV0_WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_DUALSIZE_REQ, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\

	SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh)



#define DWBC_REG_FIELD_LIST(type) \

	type WB_ENABLE;\

	type DISPCLK_R_WB_GATE_DIS;\

	type DISPCLK_G_WB_GATE_DIS;\

	type DISPCLK_G_WBSCL_GATE_DIS;\

	type WB_LB_LS_DIS;\

	type WB_LB_SD_DIS;\

	type WB_LUT_LS_DIS;\

	type CNV_WINDOW_CROP_EN;\

	type CNV_STEREO_TYPE;\

	type CNV_INTERLACED_MODE;\

	type CNV_EYE_SELECTION;\

	type CNV_STEREO_POLARITY;\

	type CNV_INTERLACED_FIELD_ORDER;\

	type CNV_STEREO_SPLIT;\

	type CNV_NEW_CONTENT;\

	type CNV_FRAME_CAPTURE_EN;\

	type WB_SOFT_RESET;\

	type MCIF_WB_BUFMGR_ENABLE;\

	type MCIF_WB_BUF_DUALSIZE_REQ;\

	type MCIF_WB_BUFMGR_SW_INT_EN;\

	type MCIF_WB_BUFMGR_SW_INT_ACK;\

	type MCIF_WB_BUFMGR_SW_SLICE_INT_EN;\

	type MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN;\

	type MCIF_WB_BUFMGR_SW_LOCK;\

	type MCIF_WB_P_VMID;\

	type MCIF_WB_BUF_ADDR_FENCE_EN;\

	type MCIF_WB_BUF_LUMA_PITCH;\

	type MCIF_WB_BUF_CHROMA_PITCH;\

	type MCIF_WB_CLIENT_ARBITRATION_SLICE;\

	type MCIF_WB_TIME_PER_PIXEL;\

	type WM_CHANGE_ACK_FORCE_ON;\

	type MCIF_WB_CLI_WATERMARK_MASK;\

	type MCIF_WB_BUF_1_ADDR_Y;\

	type MCIF_WB_BUF_1_ADDR_Y_OFFSET;\

	type MCIF_WB_BUF_1_ADDR_C;\

	type MCIF_WB_BUF_1_ADDR_C_OFFSET;\

	type MCIF_WB_BUF_2_ADDR_Y;\

	type MCIF_WB_BUF_2_ADDR_Y_OFFSET;\

	type MCIF_WB_BUF_2_ADDR_C;\

	type MCIF_WB_BUF_2_ADDR_C_OFFSET;\

	type MCIF_WB_BUF_3_ADDR_Y;\

	type MCIF_WB_BUF_3_ADDR_Y_OFFSET;\

	type MCIF_WB_BUF_3_ADDR_C;\

	type MCIF_WB_BUF_3_ADDR_C_OFFSET;\

	type MCIF_WB_BUF_4_ADDR_Y;\

	type MCIF_WB_BUF_4_ADDR_Y_OFFSET;\

	type MCIF_WB_BUF_4_ADDR_C;\

	type MCIF_WB_BUF_4_ADDR_C_OFFSET;\

	type MCIF_WB_BUFMGR_VCE_LOCK_IGNORE;\

	type MCIF_WB_BUFMGR_VCE_INT_EN;\

	type MCIF_WB_BUFMGR_VCE_INT_ACK;\

	type MCIF_WB_BUFMGR_VCE_SLICE_INT_EN;\

	type MCIF_WB_BUFMGR_VCE_LOCK;\

	type MCIF_WB_BUFMGR_SLICE_SIZE;\

	type NB_PSTATE_CHANGE_REFRESH_WATERMARK;\

	type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST;\

	type NB_PSTATE_CHANGE_FORCE_ON;\

	type NB_PSTATE_ALLOW_FOR_URGENT;\

	type NB_PSTATE_CHANGE_WATERMARK_MASK;\

	type MCIF_WB_CLI_WATERMARK;\

	type MCIF_WB_CLI_CLOCK_GATER_OVERRIDE;\

	type MCIF_WB_PITCH_SIZE_WARMUP;\

	type MCIF_WB_BUF_LUMA_SIZE;\

	type MCIF_WB_BUF_CHROMA_SIZE;\



struct dcn10_dwbc_registers {

	uint32_t WB_ENABLE;

	uint32_t WB_EC_CONFIG;

	uint32_t CNV_MODE;

	uint32_t WB_SOFT_RESET;

	uint32_t MCIF_WB_BUFMGR_SW_CONTROL;

	uint32_t MCIF_WB_BUF_PITCH;

	uint32_t MCIF_WB_ARBITRATION_CONTROL;

	uint32_t MCIF_WB_SCLK_CHANGE;

	uint32_t MCIF_WB_BUF_1_ADDR_Y;

	uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET;

	uint32_t MCIF_WB_BUF_1_ADDR_C;

	uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET;

	uint32_t MCIF_WB_BUF_2_ADDR_Y;

	uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET;

	uint32_t MCIF_WB_BUF_2_ADDR_C;

	uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET;

	uint32_t MCIF_WB_BUF_3_ADDR_Y;

	uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET;

	uint32_t MCIF_WB_BUF_3_ADDR_C;

	uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET;

	uint32_t MCIF_WB_BUF_4_ADDR_Y;

	uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET;

	uint32_t MCIF_WB_BUF_4_ADDR_C;

	uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET;

	uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;

	uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK;

	uint32_t MCIF_WB_NB_PSTATE_CONTROL;

	uint32_t MCIF_WB_WATERMARK;

	uint32_t MCIF_WB_WARM_UP_CNTL;

	uint32_t MCIF_WB_BUF_LUMA_SIZE;

	uint32_t MCIF_WB_BUF_CHROMA_SIZE;

};

struct dcn10_dwbc_mask {

	DWBC_REG_FIELD_LIST(uint32_t)

};

struct dcn10_dwbc_shift {

	DWBC_REG_FIELD_LIST(uint8_t)

};

struct dcn10_dwbc {

	struct dwbc base;

	const struct dcn10_dwbc_registers *dwbc_regs;

	const struct dcn10_dwbc_shift *dwbc_shift;

	const struct dcn10_dwbc_mask *dwbc_mask;

};



void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,

		struct dc_context *ctx,

		const struct dcn10_dwbc_registers *dwbc_regs,

		const struct dcn10_dwbc_shift *dwbc_shift,

		const struct dcn10_dwbc_mask *dwbc_mask,

		int inst);



#endif



#endif

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

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drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

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