Commit 342403bc authored by Will Deacon's avatar Will Deacon
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Merge branches 'for-next/acpi', 'for-next/bpf', 'for-next/cpufeature',... 

Merge branches 'for-next/acpi', 'for-next/bpf', 'for-next/cpufeature', 'for-next/docs', 'for-next/kconfig', 'for-next/misc', 'for-next/perf', 'for-next/ptr-auth', 'for-next/sdei', 'for-next/smccc' and 'for-next/vdso' into for-next/core

ACPI and IORT updates
(Lorenzo Pieralisi)
* for-next/acpi:
  ACPI/IORT: Remove the unused __get_pci_rid()
  ACPI/IORT: Fix PMCG node single ID mapping handling
  ACPI: IORT: Add comments for not calling acpi_put_table()
  ACPI: GTDT: Put GTDT table after parsing
  ACPI: IORT: Add extra message "applying workaround" for off-by-1 issue
  ACPI/IORT: work around num_ids ambiguity
  Revert "ACPI/IORT: Fix 'Number of IDs' handling in iort_id_map()"
  ACPI/IORT: take _DMA methods into account for named components

BPF JIT optimisations for immediate value generation
(Luke Nelson)
* for-next/bpf:
  bpf, arm64: Optimize ADD,SUB,JMP BPF_K using arm64 add/sub immediates
  bpf, arm64: Optimize AND,OR,XOR,JSET BPF_K using arm64 logical immediates
  arm64: insn: Fix two bugs in encoding 32-bit logical immediates

Addition of new CPU ID register fields and removal of some benign sanity checks
(Anshuman Khandual and others)
* for-next/cpufeature: (27 commits)
  KVM: arm64: Check advertised Stage-2 page size capability
  arm64/cpufeature: Add get_arm64_ftr_reg_nowarn()
  arm64/cpuinfo: Add ID_MMFR4_EL1 into the cpuinfo_arm64 context
  arm64/cpufeature: Add remaining feature bits in ID_AA64PFR1 register
  arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 register
  arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 register
  arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register
  arm64/cpufeature: Add remaining feature bits in ID_PFR0 register
  arm64/cpufeature: Introduce ID_MMFR5 CPU register
  arm64/cpufeature: Introduce ID_DFR1 CPU register
  arm64/cpufeature: Introduce ID_PFR2 CPU register
  arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0
  arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register
  arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register
  arm64/cpufeature: Drop open encodings while extracting parange
  arm64/cpufeature: Validate hypervisor capabilities during CPU hotplug
  arm64: cpufeature: Group indexed system register definitions by name
  arm64: cpufeature: Extend comment to describe absence of field info
  arm64: drop duplicate definitions of ID_AA64MMFR0_TGRAN constants
  arm64: cpufeature: Add an overview comment for the cpufeature framework
  ...

Minor documentation tweaks for silicon errata and booting requirements
(Rob Herring and Will Deacon)
* for-next/docs:
  arm64: silicon-errata.rst: Sort the Cortex-A55 entries
  arm64: docs: Mandate that the I-cache doesn't hold stale kernel text

Minor Kconfig cleanups
(Geert Uytterhoeven)
* for-next/kconfig:
  arm64: cpufeature: Add "or" to mitigations for multiple errata
  arm64: Sort vendor-specific errata

Miscellaneous updates
(Ard Biesheuvel and others)
* for-next/misc:
  arm64: mm: Add asid_gen_match() helper
  arm64: stacktrace: Factor out some common code into on_stack()
  arm64: Call debug_traps_init() from trap_init() to help early kgdb
  arm64: cacheflush: Fix KGDB trap detection
  arm64/cpuinfo: Move device_initcall() near cpuinfo_regs_init()
  arm64: kexec_file: print appropriate variable
  arm: mm: use __pfn_to_section() to get mem_section
  arm64: Reorder the macro arguments in the copy routines
  efi/libstub/arm64: align PE/COFF sections to segment alignment
  KVM: arm64: Drop PTE_S2_MEMATTR_MASK
  arm64/kernel: Fix range on invalidating dcache for boot page tables
  arm64: set TEXT_OFFSET to 0x0 in preparation for removing it entirely
  arm64: lib: Consistently enable crc32 extension
  arm64/mm: Use phys_to_page() to access pgtable memory
  arm64: smp: Make cpus_stuck_in_kernel static
  arm64: entry: remove unneeded semicolon in el1_sync_handler()
  arm64/kernel: vmlinux.lds: drop redundant discard/keep macros
  arm64: drop GZFLAGS definition and export
  arm64: kexec_file: Avoid temp buffer for RNG seed
  arm64: rename stext to primary_entry

Perf PMU driver updates
(Tang Bin and others)
* for-next/perf:
  pmu/smmuv3: Clear IRQ affinity hint on device removal
  drivers/perf: hisi: Permit modular builds of HiSilicon uncore drivers
  drivers/perf: hisi: Fix typo in events attribute array
  drivers/perf: arm_spe_pmu: Avoid duplicate printouts
  drivers/perf: arm_dsu_pmu: Avoid duplicate printouts

Pointer authentication updates and support for vmcoreinfo
(Amit Daniel Kachhap and Mark Rutland)
* for-next/ptr-auth:
  Documentation/vmcoreinfo: Add documentation for 'KERNELPACMASK'
  arm64/crash_core: Export KERNELPACMASK in vmcoreinfo
  arm64: simplify ptrauth initialization
  arm64: remove ptrauth_keys_install_kernel sync arg

SDEI cleanup and non-critical fixes
(James Morse and others)
* for-next/sdei:
  firmware: arm_sdei: Document the motivation behind these set_fs() calls
  firmware: arm_sdei: remove unused interfaces
  firmware: arm_sdei: Put the SDEI table after using it
  firmware: arm_sdei: Drop check for /firmware/ node and always register driver

SMCCC updates and refactoring
(Sudeep Holla)
* for-next/smccc:
  firmware: smccc: Fix missing prototype warning for arm_smccc_version_init
  firmware: smccc: Add function to fetch SMCCC version
  firmware: smccc: Refactor SMCCC specific bits into separate file
  firmware: smccc: Drop smccc_version enum and use ARM_SMCCC_VERSION_1_x instead
  firmware: smccc: Add the definition for SMCCCv1.2 version/error codes
  firmware: smccc: Update link to latest SMCCC specification
  firmware: smccc: Add HAVE_ARM_SMCCC_DISCOVERY to identify SMCCC v1.1 and above

vDSO cleanup and non-critical fixes
(Mark Rutland and Vincenzo Frascino)
* for-next/vdso:
  arm64: vdso: Add --eh-frame-hdr to ldflags
  arm64: vdso: use consistent 'map' nomenclature
  arm64: vdso: use consistent 'abi' nomenclature
  arm64: vdso: simplify arch_vdso_type ifdeffery
  arm64: vdso: remove aarch32_vdso_pages[]
  arm64: vdso: Add '-Bsymbolic' to ldflags
parents 09cda9a7 fd868f14 b130a8f7 184dbc15 357dd8a2 4fc92254 10f6cd2a c0fc00ec 472de63b 269fd61e 7e9f5e66

Documentation/admin-guide/kdump/vmcoreinfo.rst

+6 −0
Original line number Diff line number Diff line
@@ -393,6 +393,12 @@ KERNELOFFSET 
The kernel randomization offset. Used to compute the page offset. If

KASLR is disabled, this value is zero.



KERNELPACMASK

-------------



The mask to extract the Pointer Authentication Code from a kernel virtual

address.



arm

===

Documentation/arm64/booting.rst

+2 −1
Original line number Diff line number Diff line
@@ -173,7 +173,8 @@ Before jumping into the kernel, the following conditions must be met: 
- Caches, MMUs



  The MMU must be off.

  Instruction cache may be on or off.

  The instruction cache may be on or off, and must not hold any stale

  entries corresponding to the loaded kernel image.

  The address range corresponding to the loaded kernel image must be

  cleaned to the PoC. In the presence of a system cache or other

  coherent masters with caches enabled, this will typically require

Documentation/arm64/silicon-errata.rst

+4 −4
Original line number Diff line number Diff line
@@ -64,6 +64,10 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A53      | #843419         | ARM64_ERRATUM_843419        |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A55      | #1024718        | ARM64_ERRATUM_1024718       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A55      | #1530923        | ARM64_ERRATUM_1530923       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A57      | #832075         | ARM64_ERRATUM_832075        |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A57      | #852523         | N/A                         |
@@ -78,8 +82,6 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A55      | #1024718        | ARM64_ERRATUM_1024718       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A76      | #1188873,1418040| ARM64_ERRATUM_1418040       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A76      | #1165522        | ARM64_ERRATUM_1165522       |
@@ -88,8 +90,6 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A76      | #1463225        | ARM64_ERRATUM_1463225       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A55      | #1530923        | ARM64_ERRATUM_1530923       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1349291        | N/A                         |

MAINTAINERS

+9 −0
Original line number Diff line number Diff line
@@ -15474,6 +15474,15 @@ M: Nicolas Pitre <nico@fluxnic.net> 
S:	Odd Fixes

F:	drivers/net/ethernet/smsc/smc91x.*









SECURE MONITOR CALL(SMC) CALLING CONVENTION (SMCCC)









M:	Mark Rutland <mark.rutland@arm.com>









M:	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>









M:	Sudeep Holla <sudeep.holla@arm.com>









L:	linux-arm-kernel@lists.infradead.org









S:	Maintained









F:	drivers/firmware/smccc/









F:	include/linux/arm-smccc.h

















SMIA AND SMIA++ IMAGE SENSOR DRIVER









M:	Sakari Ailus <sakari.ailus@linux.intel.com>









L:	linux-media@vger.kernel.org
































arch/arm64/Kconfig



+36
−36






























Original line number
Diff line number
Diff line







@@ -553,6 +553,9 @@ config ARM64_ERRATUM_1530923

















	  If unsure, say Y.



















config ARM64_WORKAROUND_REPEAT_TLBI









	bool



















config ARM64_ERRATUM_1286807









	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"









	default y








@@ -694,6 +697,35 @@ config CAVIUM_TX2_ERRATUM_219

















	  If unsure, say Y.



















config FUJITSU_ERRATUM_010001









	bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"









	default y









	help









	  This option adds a workaround for Fujitsu-A64FX erratum E#010001.









	  On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory









	  accesses may cause undefined fault (Data abort, DFSC=0b111111).









	  This fault occurs under a specific hardware condition when a









	  load/store instruction performs an address translation using:









	  case-1  TTBR0_EL1 with TCR_EL1.NFD0 == 1.









	  case-2  TTBR0_EL2 with TCR_EL2.NFD0 == 1.









	  case-3  TTBR1_EL1 with TCR_EL1.NFD1 == 1.









	  case-4  TTBR1_EL2 with TCR_EL2.NFD1 == 1.



















	  The workaround is to ensure these bits are clear in TCR_ELx.









	  The workaround only affects the Fujitsu-A64FX.



















	  If unsure, say Y.



















config HISILICON_ERRATUM_161600802









	bool "Hip07 161600802: Erroneous redistributor VLPI base"









	default y









	help









	  The HiSilicon Hip07 SoC uses the wrong redistributor base









	  when issued ITS commands such as VMOVP and VMAPP, and requires









	  a 128kB offset to be applied to the target address in this commands.



















	  If unsure, say Y.



















config QCOM_FALKOR_ERRATUM_1003









	bool "Falkor E1003: Incorrect translation due to ASID change"









	default y








@@ -705,9 +737,6 @@ config QCOM_FALKOR_ERRATUM_1003







	  is unchanged. Work around the erratum by invalidating the walk cache









	  entries for the trampoline before entering the kernel proper.



















config ARM64_WORKAROUND_REPEAT_TLBI









	bool



















config QCOM_FALKOR_ERRATUM_1009









	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"









	default y








@@ -729,25 +758,6 @@ config QCOM_QDF2400_ERRATUM_0065

















	  If unsure, say Y.



















config SOCIONEXT_SYNQUACER_PREITS









	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"









	default y









	help









	  Socionext Synquacer SoCs implement a separate h/w block to generate









	  MSI doorbell writes with non-zero values for the device ID.



















	  If unsure, say Y.



















config HISILICON_ERRATUM_161600802









	bool "Hip07 161600802: Erroneous redistributor VLPI base"









	default y









	help









	  The HiSilicon Hip07 SoC uses the wrong redistributor base









	  when issued ITS commands such as VMOVP and VMAPP, and requires









	  a 128kB offset to be applied to the target address in this commands.



















	  If unsure, say Y.



















config QCOM_FALKOR_ERRATUM_E1041









	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"









	default y








@@ -758,22 +768,12 @@ config QCOM_FALKOR_ERRATUM_E1041

















	  If unsure, say Y.



















config FUJITSU_ERRATUM_010001









	bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"









config SOCIONEXT_SYNQUACER_PREITS









	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"









	default y









	help









	  This option adds a workaround for Fujitsu-A64FX erratum E#010001.









	  On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory









	  accesses may cause undefined fault (Data abort, DFSC=0b111111).









	  This fault occurs under a specific hardware condition when a









	  load/store instruction performs an address translation using:









	  case-1  TTBR0_EL1 with TCR_EL1.NFD0 == 1.









	  case-2  TTBR0_EL2 with TCR_EL2.NFD0 == 1.









	  case-3  TTBR1_EL1 with TCR_EL1.NFD1 == 1.









	  case-4  TTBR1_EL2 with TCR_EL2.NFD1 == 1.



















	  The workaround is to ensure these bits are clear in TCR_ELx.









	  The workaround only affects the Fujitsu-A64FX.









	  Socionext Synquacer SoCs implement a separate h/w block to generate









	  MSI doorbell writes with non-zero values for the device ID.



















	  If unsure, say Y.


















































































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