Commit 33d7598d authored by Jun Lei's avatar Jun Lei Committed by Alex Deucher
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drm/amd/display: fix up reference clock abstractions 



[why]
"reference clock" is a very overloaded variable in DC and causes confusion
as there are multiple sources of reference clock, which may be different values
incorrect input values to DML will cause DCHUB to be programmed improperly
and lead to hard to debug underflow issues

[how]
instead of using ref clock everywhere, specify WHICH ref clock:
- xtalin
- dccg refclk
- dchub refclk

these are all distinct values which may not be equal

Signed-off-by: default avatarJun Lei <Jun.Lei@amd.com>
Reviewed-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: default avatarDavid Francis <David.Francis@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d74004b6

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

+1 −1
Original line number Diff line number Diff line
@@ -466,7 +466,7 @@ static void dcn_bw_calc_rq_dlg_ttu( 
	input.clks_cfg.dcfclk_mhz = v->dcfclk;

	input.clks_cfg.dispclk_mhz = v->dispclk;

	input.clks_cfg.dppclk_mhz = v->dppclk;

	input.clks_cfg.refclk_mhz = dc->res_pool->ref_clock_inKhz / 1000.0;

	input.clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;

	input.clks_cfg.socclk_mhz = v->socclk;

	input.clks_cfg.voltage = v->voltage_level;

//	dc->dml.logger = pool->base.logger;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+24 −1
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ 
#include "opp.h"

#include "timing_generator.h"

#include "transform.h"

#include "dccg.h"

#include "dchubbub.h"

#include "dpp.h"

#include "core_types.h"

#include "set_mode_types.h"
@@ -163,7 +165,28 @@ struct resource_pool *dc_create_resource_pool( 


		if (dc->ctx->dc_bios->funcs->get_firmware_info(

				dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {

				res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency;

				res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency;



				if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {

					// On FPGA these dividers are currently not configured by GDB

					res_pool->ref_clocks.dccg_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;

					res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;

				} else if (res_pool->dccg && res_pool->hubbub) {

					// If DCCG reference frequency cannot be determined (usually means not set to xtalin) then this is a critical error

					// as this value must be known for DCHUB programming

					(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

							fw_info.pll_info.crystal_frequency,

							&res_pool->ref_clocks.dccg_ref_clock_inKhz);



					// Similarly, if DCHUB reference frequency cannot be determined, then it is also a critical error

					(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,

							res_pool->ref_clocks.dccg_ref_clock_inKhz,

							&res_pool->ref_clocks.dchub_ref_clock_inKhz);

				} else {

					// Not all ASICs have DCCG sw component

					res_pool->ref_clocks.dccg_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;

					res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;

				}

			} else

				ASSERT_CRITICAL(false);

	}

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+1 −1
Original line number Diff line number Diff line
@@ -2635,7 +2635,7 @@ void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx) 
	struct mem_input *mi = pipe_ctx->plane_res.mi;

	struct dc_cursor_mi_param param = {

		.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,

		.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,

		.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,

		.viewport = pipe_ctx->plane_res.scl_data.viewport,

		.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,

		.v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+4 −4
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ void print_microsec(struct dc_context *dc_ctx, 
	struct dc_log_buffer_ctx *log_ctx,

	uint32_t ref_cycle)

{

	const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clock_inKhz / 1000;

	const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

	static const unsigned int frac = 1000;

	uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
@@ -2453,7 +2453,7 @@ static void dcn10_prepare_bandwidth( 


	hubbub1_program_watermarks(dc->res_pool->hubbub,

			&context->bw.dcn.watermarks,

			dc->res_pool->ref_clock_inKhz / 1000,

			dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,

			true);

	dcn10_stereo_hw_frame_pack_wa(dc, context);
@@ -2483,7 +2483,7 @@ static void dcn10_optimize_bandwidth( 


	hubbub1_program_watermarks(dc->res_pool->hubbub,

			&context->bw.dcn.watermarks,

			dc->res_pool->ref_clock_inKhz / 1000,

			dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,

			true);

	dcn10_stereo_hw_frame_pack_wa(dc, context);
@@ -2703,7 +2703,7 @@ static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx) 
	struct dpp *dpp = pipe_ctx->plane_res.dpp;

	struct dc_cursor_mi_param param = {

		.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,

		.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,

		.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,

		.viewport = pipe_ctx->plane_res.scl_data.viewport,

		.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,

		.v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

+2 −2
Original line number Diff line number Diff line
@@ -77,7 +77,7 @@ static unsigned int dcn10_get_hubbub_state(struct dc *dc, char *pBuf, unsigned i 
	unsigned int chars_printed = 0;

	unsigned int remaining_buffer = bufSize;



	const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clock_inKhz / 1000;

	const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

	static const unsigned int frac = 1000;



	memset(&wm, 0, sizeof(struct dcn_hubbub_wm));
@@ -115,7 +115,7 @@ static unsigned int dcn10_get_hubp_states(struct dc *dc, char *pBuf, unsigned in 
	unsigned int chars_printed = 0;

	unsigned int remaining_buffer = bufSize;



	const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clock_inKhz / 1000;

	const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

	static const unsigned int frac = 1000;



	if (invarOnly)

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