Commit 33b9108f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'spi-fix-v5.8-rc5' of... 

Merge tag 'spi-fix-v5.8-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into master

Pull spi fixes from Mark Brown:
 "A couple of small driver specific fixes for fairly minor issues"

* tag 'spi-fix-v5.8-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
  spi: spi-sun6i: sun6i_spi_transfer_one(): fix setting of clock rate
  spi: mediatek: use correct SPI_CFG2_REG MACRO
parents 8da822e8 ed7815db

drivers/spi/spi-mt65xx.c

+8 −7
Original line number Diff line number Diff line
@@ -36,7 +36,6 @@ 
#define SPI_CFG0_SCK_LOW_OFFSET           8

#define SPI_CFG0_CS_HOLD_OFFSET           16

#define SPI_CFG0_CS_SETUP_OFFSET          24

#define SPI_ADJUST_CFG0_SCK_LOW_OFFSET    16

#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET    0

#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET   16
@@ -48,6 +47,8 @@ 
#define SPI_CFG1_CS_IDLE_MASK             0xff

#define SPI_CFG1_PACKET_LOOP_MASK         0xff00

#define SPI_CFG1_PACKET_LENGTH_MASK       0x3ff0000

#define SPI_CFG2_SCK_HIGH_OFFSET          0

#define SPI_CFG2_SCK_LOW_OFFSET           16



#define SPI_CMD_ACT                  BIT(0)

#define SPI_CMD_RESUME               BIT(1)
@@ -283,7 +284,7 @@ static void mtk_spi_set_cs(struct spi_device *spi, bool enable) 
static void mtk_spi_prepare_transfer(struct spi_master *master,

				     struct spi_transfer *xfer)

{

	u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;

	u32 spi_clk_hz, div, sck_time, cs_time, reg_val;

	struct mtk_spi *mdata = spi_master_get_devdata(master);



	spi_clk_hz = clk_get_rate(mdata->spi_clk);
@@ -296,18 +297,18 @@ static void mtk_spi_prepare_transfer(struct spi_master *master, 
	cs_time = sck_time * 2;



	if (mdata->dev_comp->enhance_timing) {

		reg_val = (((sck_time - 1) & 0xffff)

			   << SPI_CFG2_SCK_HIGH_OFFSET);

		reg_val |= (((sck_time - 1) & 0xffff)

			   << SPI_CFG0_SCK_HIGH_OFFSET);

		reg_val |= (((sck_time - 1) & 0xffff)

			   << SPI_ADJUST_CFG0_SCK_LOW_OFFSET);

			   << SPI_CFG2_SCK_LOW_OFFSET);

		writel(reg_val, mdata->base + SPI_CFG2_REG);

		reg_val |= (((cs_time - 1) & 0xffff)

		reg_val = (((cs_time - 1) & 0xffff)

			   << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);

		reg_val |= (((cs_time - 1) & 0xffff)

			   << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);

		writel(reg_val, mdata->base + SPI_CFG0_REG);

	} else {

		reg_val |= (((sck_time - 1) & 0xff)

		reg_val = (((sck_time - 1) & 0xff)

			   << SPI_CFG0_SCK_HIGH_OFFSET);

		reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);

		reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);

drivers/spi/spi-sun6i.c

+6 −8
Original line number Diff line number Diff line
@@ -198,7 +198,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master, 
				  struct spi_transfer *tfr)

{

	struct sun6i_spi *sspi = spi_master_get_devdata(master);

	unsigned int mclk_rate, div, timeout;

	unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout;

	unsigned int start, end, tx_time;

	unsigned int trig_level;

	unsigned int tx_len = 0;
@@ -287,14 +287,12 @@ static int sun6i_spi_transfer_one(struct spi_master *master, 
	 * First try CDR2, and if we can't reach the expected

	 * frequency, fall back to CDR1.

	 */

	div = mclk_rate / (2 * tfr->speed_hz);

	if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {

		if (div > 0)

			div--;



		reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS;

	div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);

	div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);

	if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {

		reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;

	} else {

		div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);

		div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));

		reg = SUN6I_CLK_CTL_CDR1(div);

	}

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