Commit 33abcb1f authored by Nirmoy Das's avatar Nirmoy Das Committed by Alex Deucher
Browse files

drm/amdgpu: set compute queue priority at mqd_init 



We were changing compute ring priority while rings were being used
before every job submission which is not recommended. This patch
sets compute queue priority at mqd initialization for gfx8, gfx9 and
gfx10.

Policy: make queue 0 of each pipe as high priority compute queue

High/normal priority compute sched lists are generated from set of high/normal
priority compute queues. At context creation, entity of compute queue
get a sched list from high or normal priority depending on ctx->priority

Signed-off-by: default avatarNirmoy Das <nirmoy.das@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c1b69212

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+0 −4
Original line number Diff line number Diff line
@@ -1205,7 +1205,6 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, 
	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;

	struct drm_sched_entity *entity = p->entity;

	enum drm_sched_priority priority;

	struct amdgpu_ring *ring;

	struct amdgpu_bo_list_entry *e;

	struct amdgpu_job *job;

	uint64_t seq;
@@ -1258,9 +1257,6 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, 
	priority = job->base.s_priority;

	drm_sched_entity_push_job(&job->base, entity);



	ring = to_amdgpu_ring(entity->rq->sched);

	amdgpu_ring_priority_get(ring, priority);



	amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);



	ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

+46 −7
Original line number Diff line number Diff line
@@ -61,12 +61,24 @@ static int amdgpu_ctx_priority_permit(struct drm_file *filp, 
	return -EACCES;

}



static enum gfx_pipe_priority amdgpu_ctx_sched_prio_to_compute_prio(enum drm_sched_priority prio)

{

	switch (prio) {

	case DRM_SCHED_PRIORITY_HIGH_HW:

	case DRM_SCHED_PRIORITY_KERNEL:

		return AMDGPU_GFX_PIPE_PRIO_HIGH;

	default:

		return AMDGPU_GFX_PIPE_PRIO_NORMAL;

	}

}



static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, const u32 hw_ip, const u32 ring)

{

	struct amdgpu_device *adev = ctx->adev;

	struct amdgpu_ctx_entity *entity;

	struct drm_gpu_scheduler **scheds = NULL, *sched = NULL;

	unsigned num_scheds = 0;

	enum gfx_pipe_priority hw_prio;

	enum drm_sched_priority priority;

	int r;
@@ -85,8 +97,9 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, const u32 hw_ip, const 
			num_scheds = 1;

			break;

		case AMDGPU_HW_IP_COMPUTE:

			scheds = adev->gfx.compute_sched;

			num_scheds = adev->gfx.num_compute_sched;

			hw_prio = amdgpu_ctx_sched_prio_to_compute_prio(priority);

			scheds = adev->gfx.compute_prio_sched[hw_prio];

			num_scheds = adev->gfx.num_compute_sched[hw_prio];

			break;

		case AMDGPU_HW_IP_DMA:

			scheds = adev->sdma.sdma_sched;
@@ -628,20 +641,46 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr) 
	mutex_destroy(&mgr->lock);

}





static void amdgpu_ctx_init_compute_sched(struct amdgpu_device *adev)

{

	int num_compute_sched_normal = 0;

	int num_compute_sched_high = AMDGPU_MAX_COMPUTE_RINGS - 1;

	int i;



	/* use one drm sched array, gfx.compute_sched to store both high and

	 * normal priority drm compute schedulers */

	for (i = 0; i < adev->gfx.num_compute_rings; i++) {

		if (!adev->gfx.compute_ring[i].has_high_prio)

			adev->gfx.compute_sched[num_compute_sched_normal++] =

				&adev->gfx.compute_ring[i].sched;

		else

			adev->gfx.compute_sched[num_compute_sched_high--] =

				&adev->gfx.compute_ring[i].sched;

	}



	/* compute ring only has two priority for now */

	i = AMDGPU_GFX_PIPE_PRIO_NORMAL;

	adev->gfx.compute_prio_sched[i] = &adev->gfx.compute_sched[0];

	adev->gfx.num_compute_sched[i] = num_compute_sched_normal;



	i = AMDGPU_GFX_PIPE_PRIO_HIGH;

	adev->gfx.compute_prio_sched[i] =

		&adev->gfx.compute_sched[num_compute_sched_high - 1];

	adev->gfx.num_compute_sched[i] =

		adev->gfx.num_compute_rings - num_compute_sched_normal;

}



void amdgpu_ctx_init_sched(struct amdgpu_device *adev)

{

	int i, j;



	amdgpu_ctx_init_compute_sched(adev);

	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {

		adev->gfx.gfx_sched[i] = &adev->gfx.gfx_ring[i].sched;

		adev->gfx.num_gfx_sched++;

	}



	for (i = 0; i < adev->gfx.num_compute_rings; i++) {

		adev->gfx.compute_sched[i] = &adev->gfx.compute_ring[i].sched;

		adev->gfx.num_compute_sched++;

	}



	for (i = 0; i < adev->sdma.num_instances; i++) {

		adev->sdma.sdma_sched[i] = &adev->sdma.instance[i].ring.sched;

		adev->sdma.num_sdma_sched++;

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

+8 −0
Original line number Diff line number Diff line
@@ -192,6 +192,14 @@ static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev) 
	return adev->gfx.mec.num_mec > 1;

}



bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,

					       int queue)

{

	/* Policy: make queue 0 of each pipe as high priority compute queue */

	return (queue == 0);



}



void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)

{

	int i, queue, pipe, mec;

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

+13 −1
Original line number Diff line number Diff line
@@ -41,6 +41,15 @@ 
#define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES

#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES



enum gfx_pipe_priority {

	AMDGPU_GFX_PIPE_PRIO_NORMAL = 1,

	AMDGPU_GFX_PIPE_PRIO_HIGH,

	AMDGPU_GFX_PIPE_PRIO_MAX

};



#define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM  0

#define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM  15



struct amdgpu_mec {

	struct amdgpu_bo	*hpd_eop_obj;

	u64			hpd_eop_gpu_addr;
@@ -281,8 +290,9 @@ struct amdgpu_gfx { 
	uint32_t			num_gfx_sched;

	unsigned			num_gfx_rings;

	struct amdgpu_ring		compute_ring[AMDGPU_MAX_COMPUTE_RINGS];

	struct drm_gpu_scheduler        **compute_prio_sched[AMDGPU_GFX_PIPE_PRIO_MAX];

	struct drm_gpu_scheduler	*compute_sched[AMDGPU_MAX_COMPUTE_RINGS];

	uint32_t			num_compute_sched;

	uint32_t                        num_compute_sched[AMDGPU_GFX_PIPE_PRIO_MAX];

	unsigned			num_compute_rings;

	struct amdgpu_irq_src		eop_irq;

	struct amdgpu_irq_src		priv_reg_irq;
@@ -364,6 +374,8 @@ void amdgpu_gfx_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 
				 int *mec, int *pipe, int *queue);

bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,

				     int pipe, int queue);

bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,

					       int queue);

int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,

			       int pipe, int queue);

void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,

drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

+0 −6
Original line number Diff line number Diff line
@@ -117,12 +117,10 @@ void amdgpu_job_free_resources(struct amdgpu_job *job) 


static void amdgpu_job_free_cb(struct drm_sched_job *s_job)

{

	struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);

	struct amdgpu_job *job = to_amdgpu_job(s_job);



	drm_sched_job_cleanup(s_job);



	amdgpu_ring_priority_put(ring, s_job->s_priority);

	dma_fence_put(job->fence);

	amdgpu_sync_free(&job->sync);

	amdgpu_sync_free(&job->sched_sync);
@@ -143,7 +141,6 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity, 
		      void *owner, struct dma_fence **f)

{

	enum drm_sched_priority priority;

	struct amdgpu_ring *ring;

	int r;



	if (!f)
@@ -158,9 +155,6 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity, 
	priority = job->base.s_priority;

	drm_sched_entity_push_job(&job->base, entity);



	ring = to_amdgpu_ring(entity->rq->sched);

	amdgpu_ring_priority_get(ring, priority);



	return 0;

}

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