ARM: 7463/1: topology: Update cpu_power according to DT information

#include <linux/percpu.h>

#include <linux/node.h>

#include <linux/nodemask.h>

#include <linux/of.h>

#include <linux/sched.h>

#include <linux/slab.h>

#include <asm/cputype.h>

#include <asm/topology.h>

	per_cpu(cpu_scale, cpu) = power;

}

#ifdef CONFIG_OF

struct cpu_efficiency {

	const char *compatible;

	unsigned long efficiency;

};

/*

 * Table of relative efficiency of each processors

 * The efficiency value must fit in 20bit and the final

 * cpu_scale value must be in the range

 *   0 < cpu_scale < 3*SCHED_POWER_SCALE/2

 * in order to return at most 1 when DIV_ROUND_CLOSEST

 * is used to compute the capacity of a CPU.

 * Processors that are not defined in the table,

 * use the default SCHED_POWER_SCALE value for cpu_scale.

 */

struct cpu_efficiency table_efficiency[] = {

	{"arm,cortex-a15", 3891},

	{"arm,cortex-a7",  2048},

	{NULL, },

};

struct cpu_capacity {

	unsigned long hwid;

	unsigned long capacity;

};

struct cpu_capacity *cpu_capacity;

unsigned long middle_capacity = 1;

/*

 * Iterate all CPUs' descriptor in DT and compute the efficiency

 * (as per table_efficiency). Also calculate a middle efficiency

 * as close as possible to  (max{eff_i} - min{eff_i}) / 2

 * This is later used to scale the cpu_power field such that an

 * 'average' CPU is of middle power. Also see the comments near

 * table_efficiency[] and update_cpu_power().

 */

static void __init parse_dt_topology(void)

{

	struct cpu_efficiency *cpu_eff;

	struct device_node *cn = NULL;

	unsigned long min_capacity = (unsigned long)(-1);

	unsigned long max_capacity = 0;

	unsigned long capacity = 0;

	int alloc_size, cpu = 0;

	alloc_size = nr_cpu_ids * sizeof(struct cpu_capacity);

	cpu_capacity = (struct cpu_capacity *)kzalloc(alloc_size, GFP_NOWAIT);

	while ((cn = of_find_node_by_type(cn, "cpu"))) {

		const u32 *rate, *reg;

		int len;

		if (cpu >= num_possible_cpus())

			break;

		for (cpu_eff = table_efficiency; cpu_eff->compatible; cpu_eff++)

			if (of_device_is_compatible(cn, cpu_eff->compatible))

				break;

		if (cpu_eff->compatible == NULL)

			continue;

		rate = of_get_property(cn, "clock-frequency", &len);

		if (!rate || len != 4) {

			pr_err("%s missing clock-frequency property\n",

				cn->full_name);

			continue;

		}

		reg = of_get_property(cn, "reg", &len);

		if (!reg || len != 4) {

			pr_err("%s missing reg property\n", cn->full_name);

			continue;

		}

		capacity = ((be32_to_cpup(rate)) >> 20) * cpu_eff->efficiency;

		/* Save min capacity of the system */

		if (capacity < min_capacity)

			min_capacity = capacity;

		/* Save max capacity of the system */

		if (capacity > max_capacity)

			max_capacity = capacity;

		cpu_capacity[cpu].capacity = capacity;

		cpu_capacity[cpu++].hwid = be32_to_cpup(reg);

	}

	if (cpu < num_possible_cpus())

		cpu_capacity[cpu].hwid = (unsigned long)(-1);

	/* If min and max capacities are equals, we bypass the update of the

	 * cpu_scale because all CPUs have the same capacity. Otherwise, we

	 * compute a middle_capacity factor that will ensure that the capacity

	 * of an 'average' CPU of the system will be as close as possible to

	 * SCHED_POWER_SCALE, which is the default value, but with the

	 * constraint explained near table_efficiency[].

	 */

	if (min_capacity == max_capacity)

		cpu_capacity[0].hwid = (unsigned long)(-1);

	else if (4*max_capacity < (3*(max_capacity + min_capacity)))

		middle_capacity = (min_capacity + max_capacity)

				>> (SCHED_POWER_SHIFT+1);

	else

		middle_capacity = ((max_capacity / 3)

				>> (SCHED_POWER_SHIFT-1)) + 1;

}

/*

 * Look for a customed capacity of a CPU in the cpu_capacity table during the

 * boot. The update of all CPUs is in O(n^2) for heteregeneous system but the

 * function returns directly for SMP system.

 */

void update_cpu_power(unsigned int cpu, unsigned long hwid)

{

	unsigned int idx = 0;

	/* look for the cpu's hwid in the cpu capacity table */

	for (idx = 0; idx < num_possible_cpus(); idx++) {

		if (cpu_capacity[idx].hwid == hwid)

			break;

		if (cpu_capacity[idx].hwid == -1)

			return;

	}

	if (idx == num_possible_cpus())

		return;

	set_power_scale(cpu, cpu_capacity[idx].capacity / middle_capacity);

	printk(KERN_INFO "CPU%u: update cpu_power %lu\n",

		cpu, arch_scale_freq_power(NULL, cpu));

}

#else

static inline void parse_dt_topology(void) {}

static inline void update_cpu_power(unsigned int cpuid, unsigned int mpidr) {}

#endif

/*

 * cpu topology management

 */

 * These masks reflect the current use of the affinity levels.

 * The affinity level can be up to 16 bits according to ARM ARM

 */

#define MPIDR_HWID_BITMASK 0xFFFFFF

#define MPIDR_LEVEL0_MASK 0x3

#define MPIDR_LEVEL0_SHIFT 0

	update_siblings_masks(cpuid);

	update_cpu_power(cpuid, mpidr & MPIDR_HWID_BITMASK);

	printk(KERN_INFO "CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n",

		cpuid, cpu_topology[cpuid].thread_id,

		cpu_topology[cpuid].core_id,

		set_power_scale(cpu, SCHED_POWER_SCALE);

	}

	smp_wmb();

	parse_dt_topology();

}