Commit 33847a71 authored by Takeshi Kihara's avatar Takeshi Kihara Committed by Geert Uytterhoeven
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pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI 



This patch supports the {get,set}_io_voltage operations of SDHI.

This operates the IOCTRL30 register on the R8A77990 SoC and makes
1.8V/3.3V signal voltage switch possible.

Signed-off-by: default avatarTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: default avatarMarek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 21ac0d58

drivers/pinctrl/sh-pfc/pfc-r8a77990.c

+33 −2
Original line number Diff line number Diff line
@@ -23,8 +23,12 @@ 
	PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \

	PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \

	PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \

	PORT_GP_CFG_16(3, fn, sfx, CFG_FLAGS), \

	PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS), \

	PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \

	PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \

	PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \

	PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \

	PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \

	PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \

	PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \

	PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS)

/*
@@ -3933,6 +3937,31 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
	{ },

};



enum ioctrl_regs {

	IOCTRL30,

};



static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {

	[IOCTRL30] = { 0xe6060380, },

	{ /* sentinel */ },

};



static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,

				   u32 *pocctrl)

{

	int bit = -EINVAL;



	*pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;



	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))

		bit = pin & 0x1f;



	if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))

		bit = (pin & 0x1f) + 19;



	return bit;

}



static const struct pinmux_bias_reg pinmux_bias_regs[] = {

	{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {

		 [0] = RCAR_GP_PIN(2, 23),	/* RD# */
@@ -4183,6 +4212,7 @@ static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 
}



static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {

	.pin_to_pocctrl = r8a77990_pin_to_pocctrl,

	.get_bias = r8a77990_pinmux_get_bias,

	.set_bias = r8a77990_pinmux_set_bias,

};
@@ -4204,6 +4234,7 @@ const struct sh_pfc_soc_info r8a774c0_pinmux_info = { 


	.cfg_regs = pinmux_config_regs,

	.bias_regs = pinmux_bias_regs,

	.ioctrl_regs = pinmux_ioctrl_regs,



	.pinmux_data = pinmux_data,

	.pinmux_data_size = ARRAY_SIZE(pinmux_data),

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