Commit 335ad94c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86-cpu-2020-08-03' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 cpu updates from Ingo Molar:

 - prepare for Intel's new SERIALIZE instruction

 - enable split-lock debugging on more CPUs

 - add more Intel CPU models

 - optimize stack canary initialization a bit

 - simplify the Spectre logic a bit

* tag 'x86-cpu-2020-08-03' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/cpu: Refactor sync_core() for readability
  x86/cpu: Relocate sync_core() to sync_core.h
  x86/cpufeatures: Add enumeration for SERIALIZE instruction
  x86/split_lock: Enable the split lock feature on Sapphire Rapids and Alder Lake CPUs
  x86/cpu: Add Lakefield, Alder Lake and Rocket Lake models to the to Intel CPU family
  x86/stackprotector: Pre-initialize canary for secondary CPUs
  x86/speculation: Merge one test in spectre_v2_user_select_mitigation()
parents 4ee48103 f69ca629

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -367,6 +367,7 @@ 
#define X86_FEATURE_SRBDS_CTRL		(18*32+ 9) /* "" SRBDS mitigation MSR available */

#define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */

#define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */

#define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */

#define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */

#define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */

#define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */

arch/x86/include/asm/intel-family.h

+7 −0
Original line number Diff line number Diff line
@@ -89,8 +89,15 @@ 
#define INTEL_FAM6_COMETLAKE		0xA5

#define INTEL_FAM6_COMETLAKE_L		0xA6



#define INTEL_FAM6_ROCKETLAKE		0xA7



#define INTEL_FAM6_SAPPHIRERAPIDS_X	0x8F



/* Hybrid Core/Atom Processors */



#define	INTEL_FAM6_LAKEFIELD		0x8A

#define INTEL_FAM6_ALDERLAKE		0x97



/* "Small Core" Processors (Atom) */



#define INTEL_FAM6_ATOM_BONNELL		0x1C /* Diamondville, Pineview */

arch/x86/include/asm/processor.h

+0 −64
Original line number Diff line number Diff line
@@ -678,70 +678,6 @@ static inline unsigned int cpuid_edx(unsigned int op) 
	return edx;

}



/*

 * This function forces the icache and prefetched instruction stream to

 * catch up with reality in two very specific cases:

 *

 *  a) Text was modified using one virtual address and is about to be executed

 *     from the same physical page at a different virtual address.

 *

 *  b) Text was modified on a different CPU, may subsequently be

 *     executed on this CPU, and you want to make sure the new version

 *     gets executed.  This generally means you're calling this in a IPI.

 *

 * If you're calling this for a different reason, you're probably doing

 * it wrong.

 */

static inline void sync_core(void)

{

	/*

	 * There are quite a few ways to do this.  IRET-to-self is nice

	 * because it works on every CPU, at any CPL (so it's compatible

	 * with paravirtualization), and it never exits to a hypervisor.

	 * The only down sides are that it's a bit slow (it seems to be

	 * a bit more than 2x slower than the fastest options) and that

	 * it unmasks NMIs.  The "push %cs" is needed because, in

	 * paravirtual environments, __KERNEL_CS may not be a valid CS

	 * value when we do IRET directly.

	 *

	 * In case NMI unmasking or performance ever becomes a problem,

	 * the next best option appears to be MOV-to-CR2 and an

	 * unconditional jump.  That sequence also works on all CPUs,

	 * but it will fault at CPL3 (i.e. Xen PV).

	 *

	 * CPUID is the conventional way, but it's nasty: it doesn't

	 * exist on some 486-like CPUs, and it usually exits to a

	 * hypervisor.

	 *

	 * Like all of Linux's memory ordering operations, this is a

	 * compiler barrier as well.

	 */

#ifdef CONFIG_X86_32

	asm volatile (

		"pushfl\n\t"

		"pushl %%cs\n\t"

		"pushl $1f\n\t"

		"iret\n\t"

		"1:"

		: ASM_CALL_CONSTRAINT : : "memory");

#else

	unsigned int tmp;



	asm volatile (

		"mov %%ss, %0\n\t"

		"pushq %q0\n\t"

		"pushq %%rsp\n\t"

		"addq $8, (%%rsp)\n\t"

		"pushfq\n\t"

		"mov %%cs, %0\n\t"

		"pushq %q0\n\t"

		"pushq $1f\n\t"

		"iretq\n\t"

		"1:"

		: "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory");

#endif

}



extern void select_idle_routine(const struct cpuinfo_x86 *c);

extern void amd_e400_c1e_apic_setup(void);

arch/x86/include/asm/special_insns.h

+0 −1
Original line number Diff line number Diff line
@@ -234,7 +234,6 @@ static inline void clwb(volatile void *__p) 


#define nop() asm volatile ("nop")





#endif /* __KERNEL__ */



#endif /* _ASM_X86_SPECIAL_INSNS_H */

arch/x86/include/asm/stackprotector.h

+12 −0
Original line number Diff line number Diff line
@@ -90,6 +90,15 @@ static __always_inline void boot_init_stack_canary(void) 
#endif

}



static inline void cpu_init_stack_canary(int cpu, struct task_struct *idle)

{

#ifdef CONFIG_X86_64

	per_cpu(fixed_percpu_data.stack_canary, cpu) = idle->stack_canary;

#else

	per_cpu(stack_canary.canary, cpu) = idle->stack_canary;

#endif

}



static inline void setup_stack_canary_segment(int cpu)

{

#ifdef CONFIG_X86_32
@@ -119,6 +128,9 @@ static inline void load_stack_canary_segment(void) 
static inline void setup_stack_canary_segment(int cpu)

{ }



static inline void cpu_init_stack_canary(int cpu, struct task_struct *idle)

{ }



static inline void load_stack_canary_segment(void)

{

#ifdef CONFIG_X86_32

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