Commit 33503e9e authored by Harry Wentland's avatar Harry Wentland Committed by Alex Deucher
Browse files

drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines 



This is required for DP HBR2 test pattern

Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8c27f5c1

drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h

+8 −0
Original line number Diff line number Diff line
@@ -4552,6 +4552,14 @@ 
#define mmDP4_DP_DPHY_PRBS_CNTL                                                 0x4eb5

#define mmDP5_DP_DPHY_PRBS_CNTL                                                 0x4fb5

#define mmDP6_DP_DPHY_PRBS_CNTL                                                 0x54b5

#define mmDP_DPHY_SCRAM_CNTL                                                    0x4ab6

#define mmDP0_DP_DPHY_SCRAM_CNTL                                                0x4ab6

#define mmDP1_DP_DPHY_SCRAM_CNTL                                                0x4bb6

#define mmDP2_DP_DPHY_SCRAM_CNTL                                                0x4cb6

#define mmDP3_DP_DPHY_SCRAM_CNTL                                                0x4db6

#define mmDP4_DP_DPHY_SCRAM_CNTL                                                0x4eb6

#define mmDP5_DP_DPHY_SCRAM_CNTL                                                0x4fb6

#define mmDP6_DP_DPHY_SCRAM_CNTL                                                0x54b6

#define mmDP_DPHY_CRC_EN                                                        0x4ab7

#define mmDP0_DP_DPHY_CRC_EN                                                    0x4ab7

#define mmDP1_DP_DPHY_CRC_EN                                                    0x4bb7

drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h

+4 −0
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@@ -8690,6 +8690,10 @@ 
#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4

#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00

#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8

#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x10

#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4

#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x3ff00

#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8

#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x1

#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0

#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x10

drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h

+9 −0
Original line number Diff line number Diff line
@@ -4544,6 +4544,15 @@ 
#define mmDP6_DP_DPHY_PRBS_CNTL                                                 0x54b5

#define mmDP7_DP_DPHY_PRBS_CNTL                                                 0x56b5

#define mmDP8_DP_DPHY_PRBS_CNTL                                                 0x57b5

#define mmDP_DPHY_SCRAM_CNTL                                                    0x4ab6

#define mmDP0_DP_DPHY_SCRAM_CNTL                                                0x4ab6

#define mmDP1_DP_DPHY_SCRAM_CNTL                                                0x4bb6

#define mmDP2_DP_DPHY_SCRAM_CNTL                                                0x4cb6

#define mmDP3_DP_DPHY_SCRAM_CNTL                                                0x4db6

#define mmDP4_DP_DPHY_SCRAM_CNTL                                                0x4eb6

#define mmDP5_DP_DPHY_SCRAM_CNTL                                                0x4fb6

#define mmDP6_DP_DPHY_SCRAM_CNTL                                                0x54b6

#define mmDP8_DP_DPHY_SCRAM_CNTL                                                0x56b6

#define mmDP_DPHY_BS_SR_SWAP_CNTL                                               0x4adc

#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4adc

#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4bdc

drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h

+4 −0
Original line number Diff line number Diff line
@@ -8366,6 +8366,10 @@ 
#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4

#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00

#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8

#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x10

#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4

#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x3ff00

#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8

#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x3ff

#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0

#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x8000

drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h

+9 −0
Original line number Diff line number Diff line
@@ -5776,6 +5776,15 @@ 
#define mmDP6_DP_DPHY_PRBS_CNTL                                                 0x54b5

#define mmDP7_DP_DPHY_PRBS_CNTL                                                 0x56b5

#define mmDP8_DP_DPHY_PRBS_CNTL                                                 0x57b5

#define mmDP_DPHY_SCRAM_CNTL                                                    0x4ab6

#define mmDP0_DP_DPHY_SCRAM_CNTL                                                0x4ab6

#define mmDP1_DP_DPHY_SCRAM_CNTL                                                0x4bb6

#define mmDP2_DP_DPHY_SCRAM_CNTL                                                0x4cb6

#define mmDP3_DP_DPHY_SCRAM_CNTL                                                0x4db6

#define mmDP4_DP_DPHY_SCRAM_CNTL                                                0x4eb6

#define mmDP5_DP_DPHY_SCRAM_CNTL                                                0x4fb6

#define mmDP6_DP_DPHY_SCRAM_CNTL                                                0x54b6

#define mmDP8_DP_DPHY_SCRAM_CNTL                                                0x56b6

#define mmDP_DPHY_BS_SR_SWAP_CNTL                                               0x4adc

#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4adc

#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4bdc

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