Commit 332fbf57 authored by Shiju Jose's avatar Shiju Jose Committed by David S. Miller
Browse files

net: hns3: add handling of hw ras errors using new set of commands 



1. This patch adds handling of hw ras errors using new set of
   common commands.
2. Updated the error message tables to match the register's name and
   error status returned by the commands.

Signed-off-by: default avatarShiju Jose <shiju.jose@huawei.com>
Signed-off-by: default avatarSalil Mehta <salil.mehta@huawei.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 481a626a

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

+3 −0
Original line number Diff line number Diff line
@@ -217,6 +217,9 @@ enum hclge_opcode_type { 
	/* Error INT commands */

	HCLGE_TM_SCH_ECC_INT_EN		= 0x0829,

	HCLGE_COMMON_ECC_INT_CFG	= 0x1505,

	HCLGE_QUERY_RAS_INT_STS_BD_NUM	= 0x1510,

	HCLGE_QUERY_CLEAR_MPF_RAS_INT	= 0x1511,

	HCLGE_QUERY_CLEAR_PF_RAS_INT	= 0x1512,

	HCLGE_IGU_EGU_TNL_INT_EN	= 0x1803,

	HCLGE_IGU_COMMON_INT_EN		= 0x1806,

	HCLGE_TM_QCN_MEM_INT_CFG	= 0x1A14,

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

+319 −170

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

+9 −0
Original line number Diff line number Diff line
@@ -21,6 +21,8 @@ 
#define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK	0x0100

#define HCLGE_TQP_ECC_ERR_INT_EN	0x0FFF

#define HCLGE_TQP_ECC_ERR_INT_EN_MASK	0x0FFF

#define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK	0x0F000000

#define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN	0x0F000000

#define HCLGE_IGU_ERR_INT_EN	0x0000066F

#define HCLGE_IGU_ERR_INT_EN_MASK	0x000F

#define HCLGE_IGU_TNL_ERR_INT_EN    0x0002AABF
@@ -40,6 +42,13 @@ 
#define HCLGE_NCSI_ERR_INT_EN	0x3

#define HCLGE_NCSI_ERR_INT_TYPE	0x9



#define HCLGE_IGU_INT_MASK		GENMASK(3, 0)

#define HCLGE_IGU_EGU_TNL_INT_MASK	GENMASK(5, 0)

#define HCLGE_PPP_MPF_INT_ST3_MASK	GENMASK(5, 0)

#define HCLGE_QCN_FIFO_INT_MASK		GENMASK(17, 0)

#define HCLGE_QCN_ECC_INT_MASK		GENMASK(21, 0)

#define HCLGE_NCSI_ECC_INT_MASK		GENMASK(1, 0)



enum hclge_err_int_type {

	HCLGE_ERR_INT_MSIX = 0,

	HCLGE_ERR_INT_RAS_CE = 1,

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