Commit 332e5281 authored by Will Deacon's avatar Will Deacon
Browse files

arm64: esr: Add ESR exception class encoding for trapped ERET 



The ESR.EC encoding of 0b011010 (0x1a) describes an exception generated
by an ERET, ERETAA or ERETAB instruction as a result of a nested
virtualisation trap to EL2.

Add an encoding for this EC and a string description so that we identify
it correctly if we take one unexpectedly.

Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Acked-by: default avatarMarc Zyngier <maz@kernel.org>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent b3e089cd

arch/arm64/include/asm/esr.h

+2 −1
Original line number Diff line number Diff line
@@ -34,7 +34,8 @@ 
#define ESR_ELx_EC_SMC64	(0x17)	/* EL2 and above */

#define ESR_ELx_EC_SYS64	(0x18)

#define ESR_ELx_EC_SVE		(0x19)

/* Unallocated EC: 0x1A - 0x1E */

#define ESR_ELx_EC_ERET		(0x1a)	/* EL2 only */

/* Unallocated EC: 0x1b - 0x1E */

#define ESR_ELx_EC_IMP_DEF	(0x1f)	/* EL3 only */

#define ESR_ELx_EC_IABT_LOW	(0x20)

#define ESR_ELx_EC_IABT_CUR	(0x21)

arch/arm64/kernel/traps.c

+1 −0
Original line number Diff line number Diff line
@@ -743,6 +743,7 @@ static const char *esr_class_str[] = { 
	[ESR_ELx_EC_SMC64]		= "SMC (AArch64)",

	[ESR_ELx_EC_SYS64]		= "MSR/MRS (AArch64)",

	[ESR_ELx_EC_SVE]		= "SVE",

	[ESR_ELx_EC_ERET]		= "ERET/ERETAA/ERETAB",

	[ESR_ELx_EC_IMP_DEF]		= "EL3 IMP DEF",

	[ESR_ELx_EC_IABT_LOW]		= "IABT (lower EL)",

	[ESR_ELx_EC_IABT_CUR]		= "IABT (current EL)",

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