Commit 331b483f authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge branch 'clockevents/3.16' of... 

Merge branch 'clockevents/3.16' of git://git.linaro.org/people/daniel.lezcano/linux into timers/core

This pull request contains the following changes:

* Laurent Pinchart did a lot of modifications to prepare the DT
  support.  These modifications include a lot of cleanup (structure
  renaming, preparation to support multiple channel, kzalloc usage,
  ...) and then finishes to drop the old code to the new one.

* Jingoo Han removed the dev_err when an allocation fails because this
  error is already given by the mm subsystems.

* Matthew Leach added the ARM global timer with vexpress, enabled the
  ARM global timer with the A5 and added the definition in the DT. He
  also fixed a invalid check when looking for an usable ARM global
  timer for A9

* Maxime Ripard added the support for AllWinner A31 for sun4i and made
  the timer reset optional through the DT

* Stephen Boyd used the msm timer for the udelay

* Uwe Kleine-König fixed the non-standard 'compatible' binding for efm32

* Xiubo Li clarified the types for the clocksource_mmio_read* and
  added a new Flextimer Module (FTM) with its bindings

* Yang Wei added the 'notrace' attribute to 'read_sched_clock' for the
  dw_apb_timer
parents 309179fa 2529c3a3

Documentation/devicetree/bindings/arm/global_timer.txt

+5 −2
Original line number Original line Diff line number Diff line
@@ -4,8 +4,11 @@ 




** Timer node required properties:

** Timer node required properties:





- compatible : Should be "arm,cortex-a9-global-timer"

- compatible : should contain

		Driver supports versions r2p0 and above.

	     * "arm,cortex-a5-global-timer" for Cortex-A5 global timers.

	     * "arm,cortex-a9-global-timer" for Cortex-A9 global

	         timers or any compatible implementation. Note: driver

	         supports versions r2p0 and above.





- interrupts : One interrupt to each core

- interrupts : One interrupt to each core

Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt

+4 −0
Original line number Original line Diff line number Diff line
@@ -9,6 +9,9 @@ Required properties: 
		one)

		one)

- clocks: phandle to the source clock (usually the AHB clock)

- clocks: phandle to the source clock (usually the AHB clock)





Optionnal properties:

- resets: phandle to a reset controller asserting the timer



Example:

Example:





timer@01c60000 {

timer@01c60000 {
@@ -19,4 +22,5 @@ timer@01c60000 { 
		     <0 53 1>,

		     <0 53 1>,

		     <0 54 1>;

		     <0 54 1>;

	clocks = <&ahb1_gates 19>;

	clocks = <&ahb1_gates 19>;

	resets = <&ahb1rst 19>;

};
 
};

Documentation/devicetree/bindings/timer/efm32,timer.txt→Documentation/devicetree/bindings/timer/energymicro,efm32-timer.txt

+2 −2
Original line number Original line Diff line number Diff line
@@ -6,7 +6,7 @@ channels and can be used as PWM or Quadrature Decoder. Available clock sources 
are the cpu's HFPERCLK (with a 10-bit prescaler) or an external pin.

are the cpu's HFPERCLK (with a 10-bit prescaler) or an external pin.





Required properties:

Required properties:

- compatible : Should be efm32,timer

- compatible : Should be "energymicro,efm32-timer"

- reg : Address and length of the register set

- reg : Address and length of the register set

- clocks : Should contain a reference to the HFPERCLK

- clocks : Should contain a reference to the HFPERCLK
@@ -16,7 +16,7 @@ Optional properties: 
Example:

Example:





timer@40010c00 {

timer@40010c00 {

	compatible = "efm32,timer";

	compatible = "energymicro,efm32-timer";

	reg = <0x40010c00 0x400>;

	reg = <0x40010c00 0x400>;

	interrupts = <14>;

	interrupts = <14>;

	clocks = <&cmu clk_HFPERCLKTIMER3>;

	clocks = <&cmu clk_HFPERCLKTIMER3>;

Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt

0 → 100644
+31 −0
Original line number Original line Diff line number Diff line 
Freescale FlexTimer Module (FTM) Timer



Required properties:



- compatible : should be "fsl,ftm-timer"

- reg : Specifies base physical address and size of the register sets for the

  clock event device and clock source device.

- interrupts : Should be the clock event device interrupt.

- clocks : The clocks provided by the SoC to drive the timer, must contain an

  entry for each entry in clock-names.

- clock-names : Must include the following entries:

  o "ftm-evt"

  o "ftm-src"

  o "ftm-evt-counter-en"

  o "ftm-src-counter-en"

- big-endian: One boolean property, the big endian mode will be in use if it is

  present, or the little endian mode will be in use for all the device registers.



Example:

ftm: ftm@400b8000 {

	compatible = "fsl,ftm-timer";

	reg = <0x400b8000 0x1000 0x400b9000 0x1000>;

	interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;

	clock-names = "ftm-evt", "ftm-src",

		"ftm-evt-counter-en", "ftm-src-counter-en";

	clocks = <&clks VF610_CLK_FTM2>,

		<&clks VF610_CLK_FTM3>,

		<&clks VF610_CLK_FTM2_EXT_FIX_EN>,

		<&clks VF610_CLK_FTM3_EXT_FIX_EN>;

	big-endian;

};

arch/arm/boot/dts/sun6i-a31.dtsi

+11 −0
Original line number Original line Diff line number Diff line
@@ -428,6 +428,17 @@ 
			status = "disabled";

			status = "disabled";

		};

		};





		timer@01c60000 {

			compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";

			reg = <0x01c60000 0x1000>;

			interrupts = <0 51 4>,

				     <0 52 4>,

				     <0 53 4>,

				     <0 54 4>;

			clocks = <&ahb1_gates 19>;

			resets = <&ahb1_rst 19>;

		};



		spi0: spi@01c68000 {

		spi0: spi@01c68000 {

			compatible = "allwinner,sun6i-a31-spi";

			compatible = "allwinner,sun6i-a31-spi";

			reg = <0x01c68000 0x1000>;

			reg = <0x01c68000 0x1000>;

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