Commit 330a5a46 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'imx-fixes-5.4' of... 

Merge tag 'imx-fixes-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes

i.MX fixes for 5.4:
 - Re-enable SNVS power key for imx6q-logicpd board which was accidentally
   disabled by a SoC level change.
 - Fix I2C switches on vf610-zii-scu4-aib board by specifying property
   i2c-mux-idle-disconnect.
 - A fix on imx-scu API that reads UID from firmware to avoid kernel NULL
   pointer dump.
 - A series from Anson to correct i.MX7 GPT and i.MX8 USDHC IPG clock.
 - A fix on DRM_MSM Kconfig regression on i.MX5 by adding the option
   explicitly into imx_v6_v7_defconfig.
 - Fix ARM regulator states issue for zii-ultra board, which is impacting
   stability of the board.
 - A correction on CPU core idle state name for LayerScape LX2160A SoC.

* tag 'imx-fixes-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: imx_v6_v7_defconfig: Enable CONFIG_DRM_MSM
  arm64: dts: imx8mn: Use correct clock for usdhc's ipg clk
  arm64: dts: imx8mm: Use correct clock for usdhc's ipg clk
  arm64: dts: imx8mq: Use correct clock for usdhc's ipg clk
  ARM: dts: imx7s: Correct GPT's ipg clock source
  ARM: dts: vf610-zii-scu4-aib: Specify 'i2c-mux-idle-disconnect'
  ARM: dts: imx6q-logicpd: Re-Enable SNVS power key
  arm64: dts: lx2160a: Correct CPU core idle state name
  arm64: dts: zii-ultra: fix ARM regulator states
  soc: imx: imx-scu: Getting UID from SCU should have response

Link: https://lore.kernel.org/r/20191017141851.GA22506@dragon


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 279296ed 95993238

arch/arm/boot/dts/imx6-logicpd-som.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -207,6 +207,10 @@ 
	vin-supply = <&sw1c_reg>;

};



&snvs_poweroff {

	status = "okay";

};



&iomuxc {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_hog>;

arch/arm/boot/dts/imx7s.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -448,7 +448,7 @@ 
				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";

				reg = <0x302d0000 0x10000>;

				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX7D_CLK_DUMMY>,

				clocks = <&clks IMX7D_GPT1_ROOT_CLK>,

					 <&clks IMX7D_GPT1_ROOT_CLK>;

				clock-names = "ipg", "per";

			};
@@ -457,7 +457,7 @@ 
				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";

				reg = <0x302e0000 0x10000>;

				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX7D_CLK_DUMMY>,

				clocks = <&clks IMX7D_GPT2_ROOT_CLK>,

					 <&clks IMX7D_GPT2_ROOT_CLK>;

				clock-names = "ipg", "per";

				status = "disabled";
@@ -467,7 +467,7 @@ 
				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";

				reg = <0x302f0000 0x10000>;

				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX7D_CLK_DUMMY>,

				clocks = <&clks IMX7D_GPT3_ROOT_CLK>,

					 <&clks IMX7D_GPT3_ROOT_CLK>;

				clock-names = "ipg", "per";

				status = "disabled";
@@ -477,7 +477,7 @@ 
				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";

				reg = <0x30300000 0x10000>;

				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX7D_CLK_DUMMY>,

				clocks = <&clks IMX7D_GPT4_ROOT_CLK>,

					 <&clks IMX7D_GPT4_ROOT_CLK>;

				clock-names = "ipg", "per";

				status = "disabled";

arch/arm/boot/dts/vf610-zii-scu4-aib.dts

+2 −0
Original line number Diff line number Diff line
@@ -602,6 +602,7 @@ 
		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x70>;

		i2c-mux-idle-disconnect;



		sff0_i2c: i2c@1 {

			#address-cells = <1>;
@@ -640,6 +641,7 @@ 
		reg = <0x71>;

		#address-cells = <1>;

		#size-cells = <0>;

		i2c-mux-idle-disconnect;



		sff5_i2c: i2c@1 {

			#address-cells = <1>;

arch/arm/configs/imx_v6_v7_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -276,6 +276,7 @@ CONFIG_VIDEO_OV5640=m 
CONFIG_VIDEO_OV5645=m

CONFIG_IMX_IPUV3_CORE=y

CONFIG_DRM=y

CONFIG_DRM_MSM=y

CONFIG_DRM_PANEL_LVDS=y

CONFIG_DRM_PANEL_SIMPLE=y

CONFIG_DRM_PANEL_SEIKO_43WVF1G=y

arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi

+18 −18
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster0_l2>;

			cpu-idle-states = <&cpu_pw20>;

			cpu-idle-states = <&cpu_pw15>;

		};



		cpu@1 {
@@ -49,7 +49,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster0_l2>;

			cpu-idle-states = <&cpu_pw20>;

			cpu-idle-states = <&cpu_pw15>;

		};



		cpu@100 {
@@ -65,7 +65,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster1_l2>;

			cpu-idle-states = <&cpu_pw20>;

			cpu-idle-states = <&cpu_pw15>;

		};



		cpu@101 {
@@ -81,7 +81,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster1_l2>;

			cpu-idle-states = <&cpu_pw20>;

			cpu-idle-states = <&cpu_pw15>;

		};



		cpu@200 {
@@ -97,7 +97,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster2_l2>;

			cpu-idle-states = <&cpu_pw20>;

			cpu-idle-states = <&cpu_pw15>;

		};



		cpu@201 {
@@ -113,7 +113,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster2_l2>;

			cpu-idle-states = <&cpu_pw20>;

			cpu-idle-states = <&cpu_pw15>;

		};



		cpu@300 {
@@ -129,7 +129,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster3_l2>;

			cpu-idle-states = <&cpu_pw20>;

			cpu-idle-states = <&cpu_pw15>;

		};



		cpu@301 {
@@ -145,7 +145,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster3_l2>;

			cpu-idle-states = <&cpu_pw20>;

			cpu-idle-states = <&cpu_pw15>;

		};



		cpu@400 {
@@ -161,7 +161,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster4_l2>;

			cpu-idle-states = <&cpu_pw20>;

			cpu-idle-states = <&cpu_pw15>;

		};



		cpu@401 {
@@ -177,7 +177,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster4_l2>;

			cpu-idle-states = <&cpu_pw20>;

			cpu-idle-states = <&cpu_pw15>;

		};



		cpu@500 {
@@ -193,7 +193,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster5_l2>;

			cpu-idle-states = <&cpu_pw20>;

			cpu-idle-states = <&cpu_pw15>;

		};



		cpu@501 {
@@ -209,7 +209,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster5_l2>;

			cpu-idle-states = <&cpu_pw20>;

			cpu-idle-states = <&cpu_pw15>;

		};



		cpu@600 {
@@ -225,7 +225,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster6_l2>;

			cpu-idle-states = <&cpu_pw20>;

			cpu-idle-states = <&cpu_pw15>;

		};



		cpu@601 {
@@ -241,7 +241,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster6_l2>;

			cpu-idle-states = <&cpu_pw20>;

			cpu-idle-states = <&cpu_pw15>;

		};



		cpu@700 {
@@ -257,7 +257,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster7_l2>;

			cpu-idle-states = <&cpu_pw20>;

			cpu-idle-states = <&cpu_pw15>;

		};



		cpu@701 {
@@ -273,7 +273,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster7_l2>;

			cpu-idle-states = <&cpu_pw20>;

			cpu-idle-states = <&cpu_pw15>;

		};



		cluster0_l2: l2-cache0 {
@@ -340,9 +340,9 @@ 
			cache-level = <2>;

		};



		cpu_pw20: cpu-pw20 {

		cpu_pw15: cpu-pw15 {

			compatible = "arm,idle-state";

			idle-state-name = "PW20";

			idle-state-name = "PW15";

			arm,psci-suspend-param = <0x0>;

			entry-latency-us = <2000>;

			exit-latency-us = <2000>;

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