Commit 32dfc773 authored by Kunihiko Hayashi's avatar Kunihiko Hayashi Committed by Masahiro Yamada
Browse files

arm64: dts: uniphier: Add PCIe host controller and PHY nodes 



Add PCIe host controller and PHY nodes. This supports for LD20, PXs3 and
their boards.

This node defines PCIe memory, I/O, and config spaces as follows.

  MEM: 20000000-2ffdffff (255MB)
  I/O: 2ffe0000-2ffeffff ( 64KB)
  CFG: 2fff0000-2fffffff ( 64KB)

Signed-off-by: default avatarKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
parent 1c7fc5cb

arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi

+47 −0
Original line number Diff line number Diff line
@@ -869,6 +869,53 @@ 
			};

		};



		pcie: pcie@66000000 {

			compatible = "socionext,uniphier-pcie", "snps,dw-pcie";

			status = "disabled";

			reg-names = "dbi", "link", "config";

			reg = <0x66000000 0x1000>, <0x66010000 0x10000>,

			      <0x2fff0000 0x10000>;

			#address-cells = <3>;

			#size-cells = <2>;

			clocks = <&sys_clk 24>;

			resets = <&sys_rst 24>;

			num-lanes = <1>;

			num-viewport = <1>;

			bus-range = <0x0 0xff>;

			device_type = "pci";

			ranges =

			/* downstream I/O */

				<0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,

			/* non-prefetchable memory */

				<0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;

			#interrupt-cells = <1>;

			interrupt-names = "dma", "msi";

			interrupts = <0 224 4>, <0 225 4>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0 0 0 1 &pcie_intc 0>,	/* INTA */

					<0 0 0 2 &pcie_intc 1>,	/* INTB */

					<0 0 0 3 &pcie_intc 2>,	/* INTC */

					<0 0 0 4 &pcie_intc 3>;	/* INTD */

			phy-names = "pcie-phy";

			phys = <&pcie_phy>;



			pcie_intc: legacy-interrupt-controller {

				interrupt-controller;

				#interrupt-cells = <1>;

				interrupt-parent = <&gic>;

				interrupts = <0 226 4>;

			};

		};



		pcie_phy: phy@66038000 {

			compatible = "socionext,uniphier-ld20-pcie-phy";

			reg = <0x66038000 0x4000>;

			#phy-cells = <0>;

			clocks = <&sys_clk 24>;

			resets = <&sys_rst 24>;

			socionext,syscon = <&soc_glue>;

		};



		nand: nand@68000000 {

			compatible = "socionext,uniphier-denali-nand-v5b";

			status = "disabled";

arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts

+4 −0
Original line number Diff line number Diff line
@@ -112,3 +112,7 @@ 
&usb1 {

	status = "okay";

};



&pcie {

	status = "okay";

};

arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi

+47 −0
Original line number Diff line number Diff line
@@ -727,6 +727,53 @@ 
			};

		};



		pcie: pcie@66000000 {

			compatible = "socionext,uniphier-pcie", "snps,dw-pcie";

			status = "disabled";

			reg-names = "dbi", "link", "config";

			reg = <0x66000000 0x1000>, <0x66010000 0x10000>,

			      <0x2fff0000 0x10000>;

			#address-cells = <3>;

			#size-cells = <2>;

			clocks = <&sys_clk 24>;

			resets = <&sys_rst 24>;

			num-lanes = <1>;

			num-viewport = <1>;

			bus-range = <0x0 0xff>;

			device_type = "pci";

			ranges =

			/* downstream I/O */

				<0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,

			/* non-prefetchable memory */

				<0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;

			#interrupt-cells = <1>;

			interrupt-names = "dma", "msi";

			interrupts = <0 224 4>, <0 225 4>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0 0 0 1 &pcie_intc 0>,	/* INTA */

					<0 0 0 2 &pcie_intc 1>,	/* INTB */

					<0 0 0 3 &pcie_intc 2>,	/* INTC */

					<0 0 0 4 &pcie_intc 3>;	/* INTD */

			phy-names = "pcie-phy";

			phys = <&pcie_phy>;



			pcie_intc: legacy-interrupt-controller {

				interrupt-controller;

				#interrupt-cells = <1>;

				interrupt-parent = <&gic>;

				interrupts = <0 226 4>;

			};

		};



		pcie_phy: phy@66038000 {

			compatible = "socionext,uniphier-pxs3-pcie-phy";

			reg = <0x66038000 0x4000>;

			#phy-cells = <0>;

			clocks = <&sys_clk 24>;

			resets = <&sys_rst 24>;

			socionext,syscon = <&soc_glue>;

		};



		nand: nand@68000000 {

			compatible = "socionext,uniphier-denali-nand-v5b";

			status = "disabled";

CRA Git | Maintained and supported by SUSTech CRA and CCSE