KVM: nVMX: Expose VMCS shadowing to L1 guest (32c7acf0) · Commits · 戴 / test

Expose VMCS shadowing to L1 as a VMX capability of the virtual CPU, whether or not VMCS shadowing is supported by the physical CPU. (VMCS shadowing emulation) Shadowed VMREADs and VMWRITEs from L2 are handled by L0, without a VM-exit to L1. Signed-off-by:

Liran Alon <liran.alon@oracle.com> Signed-off-by:

Jim Mattson <jmattson@google.com> Signed-off-by:

Paolo Bonzini <pbonzini@redhat.com>

arch/x86/kvm/vmx.c

+9 −0

Original line number	Diff line number	Diff line
		@@ -3308,6 +3308,12 @@ static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, bool apicv)
		SECONDARY_EXEC_APIC_REGISTER_VIRT \|
		SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY \|
		SECONDARY_EXEC_WBINVD_EXITING;
		/*
		* We can emulate "VMCS shadowing," even if the hardware
		* doesn't support it.
		*/
		msrs->secondary_ctls_high \|=
		SECONDARY_EXEC_SHADOW_VMCS;

		if (enable_ept) {
		/* nested EPT: emulate EPT also to L1 */
		@@ -11550,6 +11556,9 @@ static int prepare_vmcs02(struct kvm_vcpu vcpu, struct vmcs12 vmcs12,
		exec_control \|= vmcs12_exec_ctrl;
		}

		/* VMCS shadowing for L2 is emulated for now */
		exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;

		if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
		vmcs_write16(GUEST_INTR_STATUS,
		vmcs12->guest_intr_status);

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