Commit 32c7553f authored Jan 30, 2008 by Andi Kleen Committed by Ingo Molnar Jan 30, 2008

x86: remove explicit C3 TSC check on 64bit



Trust the ACPI code to disable TSC instead when C3 is used.

AMD Fam10h does not disable TSC in any C states so the
check was incorrect there anyways after the change
to handle this like Intel on AMD too.

This allows to use the TSC when C3 is disabled in software
(acpi.max_c_state=2), but the BIOS supports it anyways.

Match i386 behaviour.

Cc: lenb@kernel.org

Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

parent 51fc97b9

arch/x86/kernel/tsc_64.c

+1 −8

Original line number	Diff line number	Diff line
		@@ -273,15 +273,8 @@ __cpuinit int unsynchronized_tsc(void)
		return 1;
		#endif

		if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
		#ifdef CONFIG_ACPI
		/* But TSC doesn't tick in C3 so don't use it there */
		if (acpi_gbl_FADT.header.length > 0 &&
		acpi_gbl_FADT.C3latency < 1000)
		return 1;
		#endif
		if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
		return 0;
		}

		/* Assume multi socket systems are not synchronized */
		return num_present_cpus() > 1;

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