spi: tegra114: terminate dma and reset on transfer timeout (32bd1a95) · Commits · 戴 / test

Fixes: terminate DMA and perform controller reset on transfer timeout to clear the FIFO's and errors. Signed-off-by:

drivers/spi/spi-tegra114.c

+9 −0

Original line number	Diff line number	Diff line
		@@ -869,7 +869,16 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
		if (WARN_ON(ret == 0)) {
		dev_err(tspi->dev,
		"spi transfer timeout, err %d\n", ret);
		if (tspi->is_curr_dma_xfer &&
		(tspi->cur_direction & DATA_DIR_TX))
		dmaengine_terminate_all(tspi->tx_dma_chan);
		if (tspi->is_curr_dma_xfer &&
		(tspi->cur_direction & DATA_DIR_RX))
		dmaengine_terminate_all(tspi->rx_dma_chan);
		ret = -EIO;
		reset_control_assert(tspi->rst);
		udelay(2);
		reset_control_deassert(tspi->rst);
		goto complete_xfer;
		}