Commit 32adc19d authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'zynq-cleanup-for-3.15-v2' of git://git.xilinx.com/linux-xlnx into next/cleanup2 

Merge "arm: Xilinx Zynq cleanup patches for v3.15" from Michal Simek:

- Redesign SLCR initialization to enable
  driver developing which targets SLCR space

* tag 'zynq-cleanup-for-3.15-v2' of git://git.xilinx.com/linux-xlnx

:
  ARM: zynq: Add waituart implementation
  ARM: zynq: Move of_clk_init from clock driver
  ARM: zynq: Introduce zynq_slcr_unlock()
  ARM: zynq: Add and use zynq_slcr_read/write() helper functions
  ARM: zynq: Make zynq_slcr_base static
  ARM: zynq: Map I/O memory on clkc init
  ARM: zynq: Hang iomapped slcr address on device_node
  ARM: zynq: Split slcr in two parts
  ARM: zynq: Move clock_init from slcr to common
  arm: dt: zynq: Add fclk-enable property to clkc node

[Arnd: remove SOC_BUS support from pull request]

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 22673b71 1a259251

Documentation/devicetree/bindings/clock/zynq-7000.txt

+3 −1
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ for all clock consumers of PS clocks. 
Required properties:

 - #clock-cells : Must be 1

 - compatible : "xlnx,ps7-clkc"

 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >

 - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ

		      (usually 33 MHz oscillators are used for Zynq platforms)

 - clock-output-names : List of strings used to name the clock outputs. Shall be
@@ -87,10 +88,11 @@ Clock outputs: 
 47: dbg_apb



Example:

	clkc: clkc {

	clkc: clkc@100 {

		#clock-cells = <1>;

		compatible = "xlnx,ps7-clkc";

		ps-clk-frequency = <33333333>;

		reg = <0x100 0x100>;

		clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",

				"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",

				"dci", "lqspi", "smc", "pcap", "gem0", "gem1",

arch/arm/boot/dts/zynq-7000.dtsi

+21 −22
Original line number Diff line number Diff line
@@ -123,17 +123,16 @@ 
		} ;



		slcr: slcr@f8000000 {

			compatible = "xlnx,zynq-slcr";

			reg = <0xF8000000 0x1000>;



			clocks {

			#address-cells = <1>;

				#size-cells = <0>;



				clkc: clkc {

			#size-cells = <1>;

			compatible = "xlnx,zynq-slcr", "syscon";

			reg = <0xF8000000 0x1000>;

			ranges;

			clkc: clkc@100 {

				#clock-cells = <1>;

				compatible = "xlnx,ps7-clkc";

				ps-clk-frequency = <33333333>;

				fclk-enable = <0>;

				clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",

						"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",

						"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
@@ -145,7 +144,7 @@ 
						"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",

						"gpio_aper", "lqspi_aper", "smc_aper", "swdt",

						"dbg_trc", "dbg_apb";

				};

				reg = <0x100 0x100>;

			};

		};

arch/arm/include/debug/zynq.S

+3 −0
Original line number Diff line number Diff line
@@ -42,6 +42,9 @@ 
		.endm



		.macro	waituart,rd,rx

1001:		ldr	\rd, [\rx, #UART_SR_OFFSET]

		tst	\rd, #UART_SR_TXEMPTY

		beq	1001b

		.endm



		.macro	busyuart,rd,rx

arch/arm/mach-zynq/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -14,5 +14,6 @@ config ARCH_ZYNQ 
	select SPARSE_IRQ

	select CADENCE_TTC_TIMER

	select ARM_GLOBAL_TIMER

	select MFD_SYSCON

	help

	  Support for Xilinx Zynq ARM Cortex A9 Platform

arch/arm/mach-zynq/common.c

+7 −1
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
#include <linux/cpumask.h>

#include <linux/platform_device.h>

#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/clk/zynq.h>

#include <linux/clocksource.h>

#include <linux/of_address.h>
@@ -72,11 +73,16 @@ static void __init zynq_init_machine(void) 
	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);



	platform_device_register(&zynq_cpuidle_device);



	zynq_slcr_init();

}



static void __init zynq_timer_init(void)

{

	zynq_slcr_init();

	zynq_early_slcr_init();



	zynq_clock_init();

	of_clk_init(NULL);

	clocksource_of_init();

}

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