Commit 32a3e635 authored by Marc Zyngier's avatar Marc Zyngier Committed by Catalin Marinas
Browse files

arm64: compat: Add CNTFRQ trap handler 



Just like CNTVCT, we need to handle userspace trapping into the
kernel if we're decided that the timer wasn't fit for purpose...
64bit userspace is already dealt with, but we're missing the
equivalent compat handling.

Reviewed-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 50de013d

arch/arm64/include/asm/esr.h

+3 −0
Original line number Diff line number Diff line
@@ -318,6 +318,9 @@ 
#define ESR_ELx_CP15_64_ISS_SYS_CNTVCT	(ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \

					 ESR_ELx_CP15_64_ISS_DIR_READ)



#define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ	(ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\

					 ESR_ELx_CP15_32_ISS_DIR_READ)



#ifndef __ASSEMBLY__

#include <asm/types.h>

arch/arm64/kernel/traps.c

+13 −0
Original line number Diff line number Diff line
@@ -625,7 +625,20 @@ static void arm64_compat_skip_faulting_instruction(struct pt_regs *regs, 
	arm64_skip_faulting_instruction(regs, sz);

}



static void compat_cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)

{

	int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT;



	pt_regs_write_reg(regs, reg, arch_timer_get_rate());

	arm64_compat_skip_faulting_instruction(regs, 4);

}



static struct sys64_hook cp15_32_hooks[] = {

	{

		.esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK,

		.esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ,

		.handler = compat_cntfrq_read_handler,

	},

	{},

};

CRA Git | Maintained and supported by SUSTech CRA and CCSE