Commit 3280e8b0 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915/bdw: Extract rp_state_caps logic 



We have a need for duplicated parsing of the RP_STATE_CAPS register (and
the setting of the associated fields). To reuse some code, we can
extract the function into a simple helper.

This patch also addresses the fact that we missed doing this for gen8,
something we should have done anyway.

This could be two patches, one to extract, and one to add gen8, but it's
trivial enough that I think one is fine. I will accept a request to
split it. Please notice the fix addressed by v2 below.

Valleyview is left untouched because it is different.

v2: Logically rebased on top of
commit dd0a1aa1
Author: Jeff McGee <jeff.mcgee@intel.com>
Date:   Tue Feb 4 11:32:31 2014 -0600

    drm/i915: Restore rps/rc6 on reset

Note with the above change the fix for gen8 is also handled (which was
not the case in Jeff's original patch).

Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent f9bdc585

drivers/gpu/drm/i915/intel_pm.c

+23 −17
Original line number Diff line number Diff line
@@ -3242,6 +3242,27 @@ static void gen6_enable_rps_interrupts(struct drm_device *dev) 
	spin_unlock_irq(&dev_priv->irq_lock);

}



static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)

{

	/* All of these values are in units of 50MHz */

	dev_priv->rps.cur_freq		= 0;

	/* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */

	dev_priv->rps.rp1_freq		= (rp_state_cap >>  8) & 0xff;

	dev_priv->rps.rp0_freq		= (rp_state_cap >>  0) & 0xff;

	dev_priv->rps.min_freq		= (rp_state_cap >> 16) & 0xff;

	/* XXX: only BYT has a special efficient freq */

	dev_priv->rps.efficient_freq	= dev_priv->rps.rp1_freq;

	/* hw_max = RP0 until we check for overclocking */

	dev_priv->rps.max_freq		= dev_priv->rps.rp0_freq;



	/* Preserve min/max settings in case of re-init */

	if (dev_priv->rps.max_freq_softlimit == 0)

		dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;



	if (dev_priv->rps.min_freq_softlimit == 0)

		dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;

}



static void gen8_enable_rps(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3260,6 +3281,7 @@ static void gen8_enable_rps(struct drm_device *dev) 
	I915_WRITE(GEN6_RC_CONTROL, 0);



	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);

	parse_rp_state_cap(dev_priv, rp_state_cap);



	/* 2b: Program RC6 thresholds.*/

	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
@@ -3348,23 +3370,7 @@ static void gen6_enable_rps(struct drm_device *dev) 
	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);

	gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);



	/* All of these values are in units of 50MHz */

	dev_priv->rps.cur_freq		= 0;

	/* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */

	dev_priv->rps.rp1_freq		= (rp_state_cap >>  8) & 0xff;

	dev_priv->rps.rp0_freq		= (rp_state_cap >>  0) & 0xff;

	dev_priv->rps.min_freq		= (rp_state_cap >> 16) & 0xff;

	/* XXX: only BYT has a special efficient freq */

	dev_priv->rps.efficient_freq	= dev_priv->rps.rp1_freq;

	/* hw_max = RP0 until we check for overclocking */

	dev_priv->rps.max_freq		= dev_priv->rps.rp0_freq;



	/* Preserve min/max settings in case of re-init */

	if (dev_priv->rps.max_freq_softlimit == 0)

		dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;



	if (dev_priv->rps.min_freq_softlimit == 0)

		dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;

	parse_rp_state_cap(dev_priv, rp_state_cap);



	/* disable the counters and set deterministic thresholds */

	I915_WRITE(GEN6_RC_CONTROL, 0);

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