Commit 3275a71e authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-next-5.5-2019-10-09' of git://people.freedesktop.org/~agd5f/linux into drm-next 



drm-next-5.5-2019-10-09:

amdgpu:
- Additional RAS enablement for vega20
- RAS page retirement and bad page storage in EEPROM
- No GPU reset with unrecoverable RAS errors
- Reserve vram for page tables rather than trying to evict
- Fix issues with GPU reset and xgmi hives
- DC i2c over aux fixes
- Direct submission for clears, PTE/PDE updates
- Improvements to help support recoverable GPU page faults
- Silence harmless SAD block messages
- Clean up code for creating a bo at a fixed location
- Initial DC HDCP support
- Lots of documentation fixes
- GPU reset for renoir
- Add IH clockgating support for soc15 asics
- Powerplay improvements
- DC MST cleanups
- Add support for MSI-X
- Misc cleanups and bug fixes

amdkfd:
- Query KFD device info by asic type rather than pci ids
- Add navi14 support
- Add renoir support
- Add navi12 support
- gfx10 trap handler improvements
- pasid cleanups
- Check against device cgroup

ttm:
- Return -EBUSY with pipelining with no_gpu_wait

radeon:
- Silence harmless SAD block messages

device_cgroup:
- Export devcgroup_check_permission

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191010041713.3412-1-alexander.deucher@amd.com
parents 2e79e22e 1cd4d9ee

Documentation/gpu/amdgpu.rst

+25 −5
Original line number Diff line number Diff line
@@ -79,12 +79,32 @@ AMDGPU XGMI Support 
.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

   :internal:



AMDGPU RAS debugfs control interface

====================================

AMDGPU RAS Support

==================



RAS debugfs/sysfs Control and Error Injection Interfaces

--------------------------------------------------------



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   :doc: AMDGPU RAS debugfs control interface



RAS Error Count sysfs Interface

-------------------------------



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   :doc: AMDGPU RAS sysfs Error Count Interface



RAS EEPROM debugfs Interface

----------------------------



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   :doc: AMDGPU RAS debugfs EEPROM table reset interface



RAS VRAM Bad Pages sysfs Interface

----------------------------------



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   :doc: AMDGPU RAS sysfs gpu_vram_bad_pages Interface



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   :internal:
@@ -130,11 +150,11 @@ pp_od_clk_voltage 
.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   :doc: pp_od_clk_voltage



pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

pp_dpm_*

~~~~~~~~



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   :doc: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie

   :doc: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie



pp_power_profile_mode

~~~~~~~~~~~~~~~~~~~~~

drivers/gpu/drm/amd/amdgpu/Makefile

+5 −4
Original line number Diff line number Diff line
@@ -53,8 +53,9 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ 
	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \

	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \

	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \

	amdgpu_gmc.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \

	amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o smu_v11_0_i2c.o

	amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \

	amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \

	amdgpu_umc.o smu_v11_0_i2c.o



amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
@@ -67,7 +68,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce 
amdgpu-y += \

	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \

	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \

	arct_reg_init.o navi12_reg_init.o

	arct_reg_init.o navi12_reg_init.o mxgpu_nv.o



# add DF block

amdgpu-y += \
@@ -83,7 +84,7 @@ amdgpu-y += \ 


# add UMC block

amdgpu-y += \

	umc_v6_1.o

	umc_v6_1.o umc_v6_0.o



# add IH block

amdgpu-y += \

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+17 −67
Original line number Diff line number Diff line
@@ -73,6 +73,7 @@ 
#include "amdgpu_gmc.h"

#include "amdgpu_gfx.h"

#include "amdgpu_sdma.h"

#include "amdgpu_nbio.h"

#include "amdgpu_dm.h"

#include "amdgpu_virt.h"

#include "amdgpu_csa.h"
@@ -106,6 +107,8 @@ struct amdgpu_mgpu_info 
	uint32_t			num_apu;

};



#define AMDGPU_MAX_TIMEOUT_PARAM_LENTH	256



/*

 * Modules parameters.

 */
@@ -122,6 +125,7 @@ extern int amdgpu_disp_priority; 
extern int amdgpu_hw_i2c;

extern int amdgpu_pcie_gen2;

extern int amdgpu_msi;

extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH];

extern int amdgpu_dpm;

extern int amdgpu_fw_load_type;

extern int amdgpu_aspm;
@@ -146,11 +150,6 @@ extern uint amdgpu_sdma_phase_quantum; 
extern char *amdgpu_disable_cu;

extern char *amdgpu_virtual_display;

extern uint amdgpu_pp_feature_mask;

extern int amdgpu_ngg;

extern int amdgpu_prim_buf_per_se;

extern int amdgpu_pos_buf_per_se;

extern int amdgpu_cntl_sb_buf_per_se;

extern int amdgpu_param_buf_per_se;

extern int amdgpu_job_hang_limit;

extern int amdgpu_lbpw;

extern int amdgpu_compute_multipipe;
@@ -167,6 +166,12 @@ extern int amdgpu_mcbp; 
extern int amdgpu_discovery;

extern int amdgpu_mes;

extern int amdgpu_noretry;

extern int amdgpu_force_asic_type;

#ifdef CONFIG_HSA_AMD

extern int sched_policy;

#else

static const int sched_policy = KFD_SCHED_POLICY_HWS;

#endif



#ifdef CONFIG_DRM_AMDGPU_SI

extern int amdgpu_si_support;
@@ -425,7 +430,6 @@ struct amdgpu_fpriv { 
};



int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);

int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev);



int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,

		  unsigned size, struct amdgpu_ib *ib);
@@ -477,7 +481,6 @@ struct amdgpu_cs_parser { 
	uint64_t			bytes_moved_vis_threshold;

	uint64_t			bytes_moved;

	uint64_t			bytes_moved_vis;

	struct amdgpu_bo_list_entry	*evictable;



	/* user fence */

	struct amdgpu_bo_list_entry	uf_entry;
@@ -644,71 +647,14 @@ typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 
typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);

typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);





/*

 * amdgpu nbio functions

 *

 */

struct nbio_hdp_flush_reg {

	u32 ref_and_mask_cp0;

	u32 ref_and_mask_cp1;

	u32 ref_and_mask_cp2;

	u32 ref_and_mask_cp3;

	u32 ref_and_mask_cp4;

	u32 ref_and_mask_cp5;

	u32 ref_and_mask_cp6;

	u32 ref_and_mask_cp7;

	u32 ref_and_mask_cp8;

	u32 ref_and_mask_cp9;

	u32 ref_and_mask_sdma0;

	u32 ref_and_mask_sdma1;

	u32 ref_and_mask_sdma2;

	u32 ref_and_mask_sdma3;

	u32 ref_and_mask_sdma4;

	u32 ref_and_mask_sdma5;

	u32 ref_and_mask_sdma6;

	u32 ref_and_mask_sdma7;

};



struct amdgpu_mmio_remap {

	u32 reg_offset;

	resource_size_t bus_addr;

};



struct amdgpu_nbio_funcs {

	const struct nbio_hdp_flush_reg *hdp_flush_reg;

	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);

	u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);

	u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);

	u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);

	u32 (*get_rev_id)(struct amdgpu_device *adev);

	void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);

	void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);

	u32 (*get_memsize)(struct amdgpu_device *adev);

	void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,

			bool use_doorbell, int doorbell_index, int doorbell_size);

	void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,

				   int doorbell_index, int instance);

	void (*enable_doorbell_aperture)(struct amdgpu_device *adev,

					 bool enable);

	void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,

						  bool enable);

	void (*ih_doorbell_range)(struct amdgpu_device *adev,

				  bool use_doorbell, int doorbell_index);

	void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,

						 bool enable);

	void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,

						bool enable);

	void (*get_clockgating_state)(struct amdgpu_device *adev,

				      u32 *flags);

	void (*ih_control)(struct amdgpu_device *adev);

	void (*init_registers)(struct amdgpu_device *adev);

	void (*detect_hw_virt)(struct amdgpu_device *adev);

	void (*remap_hdp_registers)(struct amdgpu_device *adev);

};



struct amdgpu_df_funcs {

	void (*sw_init)(struct amdgpu_device *adev);

	void (*sw_fini)(struct amdgpu_device *adev);

	void (*enable_broadcast_mode)(struct amdgpu_device *adev,

				      bool enable);

	u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
@@ -921,6 +867,12 @@ struct amdgpu_device { 
	u32				cg_flags;

	u32				pg_flags;



	/* nbio */

	struct amdgpu_nbio		nbio;



	/* mmhub */

	struct amdgpu_mmhub		mmhub;



	/* gfx */

	struct amdgpu_gfx		gfx;
@@ -974,9 +926,7 @@ struct amdgpu_device { 
	/* soc15 register offset based on ip, instance and  segment */

	uint32_t 		*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];



	const struct amdgpu_nbio_funcs	*nbio_funcs;

	const struct amdgpu_df_funcs	*df_funcs;

	const struct amdgpu_mmhub_funcs	*mmhub_funcs;



	/* delayed work_func for deferring clockgating during resume */

	struct delayed_work     delayed_init_work;

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+5 −64
Original line number Diff line number Diff line
@@ -63,45 +63,10 @@ void amdgpu_amdkfd_fini(void) 


void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)

{

	const struct kfd2kgd_calls *kfd2kgd;



	switch (adev->asic_type) {

#ifdef CONFIG_DRM_AMDGPU_CIK

	case CHIP_KAVERI:

	case CHIP_HAWAII:

		kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();

		break;

#endif

	case CHIP_CARRIZO:

	case CHIP_TONGA:

	case CHIP_FIJI:

	case CHIP_POLARIS10:

	case CHIP_POLARIS11:

	case CHIP_POLARIS12:

	case CHIP_VEGAM:

		kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();

		break;

	case CHIP_VEGA10:

	case CHIP_VEGA12:

	case CHIP_VEGA20:

	case CHIP_RAVEN:

		kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();

		break;

	case CHIP_ARCTURUS:

		kfd2kgd = amdgpu_amdkfd_arcturus_get_functions();

		break;

	case CHIP_NAVI10:

	case CHIP_NAVI14:

	case CHIP_NAVI12:

		kfd2kgd = amdgpu_amdkfd_gfx_10_0_get_functions();

		break;

	default:

		dev_info(adev->dev, "kfd not supported on this ASIC\n");

		return;

	}

	bool vf = amdgpu_sriov_vf(adev);



	adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,

				      adev->pdev, kfd2kgd);

				      adev->pdev, adev->asic_type, vf);



	if (adev->kfd.dev)

		amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
@@ -202,7 +167,7 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 
					adev->doorbell_index.last_non_cp;

		}



		kgd2kfd_device_init(adev->kfd.dev, &gpu_resources);

		kgd2kfd_device_init(adev->kfd.dev, adev->ddev, &gpu_resources);

	}

}
@@ -709,38 +674,14 @@ int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm) 
	return 0;

}



struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)

{

	return NULL;

}



struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)

{

	return NULL;

}



struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)

{

	return NULL;

}



struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void)

{

	return NULL;

}



struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions(void)

{

	return NULL;

}



struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,

			      const struct kfd2kgd_calls *f2g)

			      unsigned int asic_type, bool vf)

{

	return NULL;

}



bool kgd2kfd_device_init(struct kfd_dev *kfd,

			 struct drm_device *ddev,

			 const struct kgd2kfd_shared_resources *gpu_resources)

{

	return false;

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h

+11 −8
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@ struct kgd_mem { 
	unsigned int mapped_to_gpu_memory;

	uint64_t va;



	uint32_t mapping_flags;

	uint32_t alloc_flags;



	atomic_t invalid;

	struct amdkfd_process_info *process_info;
@@ -137,12 +137,6 @@ int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine, 
void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle);

bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd);



struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void);

struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void);

struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void);

struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void);

struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions(void);



bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);



int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev);
@@ -179,10 +173,17 @@ uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd); 
uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd);

uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src);



/* Read user wptr from a specified user address space with page fault

 * disabled. The memory must be pinned and mapped to the hardware when

 * this is called in hqd_load functions, so it should never fault in

 * the first place. This resolves a circular lock dependency involving

 * four locks, including the DQM lock and mmap_sem.

 */

#define read_user_wptr(mmptr, wptr, dst)				\

	({								\

		bool valid = false;					\

		if ((mmptr) && (wptr)) {				\

			pagefault_disable();				\

			if ((mmptr) == current->mm) {			\

				valid = !get_user((dst), (wptr));	\

			} else if (current->mm == NULL) {		\
@@ -190,6 +191,7 @@ uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *s 
				valid = !get_user((dst), (wptr));	\

				unuse_mm(mmptr);			\

			}						\

			pagefault_enable();				\

		}							\

		valid;							\

	})
@@ -240,8 +242,9 @@ void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo); 
int kgd2kfd_init(void);

void kgd2kfd_exit(void);

struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,

			      const struct kfd2kgd_calls *f2g);

			      unsigned int asic_type, bool vf);

bool kgd2kfd_device_init(struct kfd_dev *kfd,

			 struct drm_device *ddev,

			 const struct kgd2kfd_shared_resources *gpu_resources);

void kgd2kfd_device_exit(struct kfd_dev *kfd);

void kgd2kfd_suspend(struct kfd_dev *kfd);

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