Commit 321b628e authored by Wangyan Wang's avatar Wangyan Wang Committed by CK Hu
Browse files

drm/mediatek: make implementation of recalc_rate() for MT2701 hdmi phy 



Recalculate the rate of this clock, by querying hardware to
make implementation of recalc_rate() to match the definition.

Signed-off-by: default avatarWangyan Wang <wangyan.wang@mediatek.com>
Signed-off-by: default avatarCK Hu <ck.hu@mediatek.com>
parent 0c24613c

drivers/gpu/drm/mediatek/mtk_hdmi_phy.c

+0 −8
Original line number Diff line number Diff line
@@ -29,14 +29,6 @@ long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate, 
	return rate;

}



unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,

				       unsigned long parent_rate)

{

	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);



	return hdmi_phy->pll_rate;

}



void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,

			     u32 bits)

{

drivers/gpu/drm/mediatek/mtk_hdmi_phy.h

+0 −2
Original line number Diff line number Diff line
@@ -50,8 +50,6 @@ void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset, 
struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);

long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,

			     unsigned long *parent_rate);

unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,

				       unsigned long parent_rate);



extern struct platform_driver mtk_hdmi_phy_driver;

extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;

drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c

+34 −4
Original line number Diff line number Diff line
@@ -79,7 +79,6 @@ static int mtk_hdmi_pll_prepare(struct clk_hw *hw) 
	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);

	usleep_range(80, 100);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
@@ -94,7 +93,6 @@ static void mtk_hdmi_pll_unprepare(struct clk_hw *hw) 
	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);

	usleep_range(80, 100);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
@@ -123,6 +121,7 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, 


	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_PREDIV_MASK);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);

	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC),

			  RG_HTPLL_IC_MASK);

	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR),
@@ -154,6 +153,39 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
	return 0;

}



static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,

					      unsigned long parent_rate)

{

	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);

	unsigned long out_rate, val;



	val = (readl(hdmi_phy->regs + HDMI_CON6)

	       & RG_HTPLL_PREDIV_MASK) >> RG_HTPLL_PREDIV;

	switch (val) {

	case 0x00:

		out_rate = parent_rate;

		break;

	case 0x01:

		out_rate = parent_rate / 2;

		break;

	default:

		out_rate = parent_rate / 4;

		break;

	}



	val = (readl(hdmi_phy->regs + HDMI_CON6)

	       & RG_HTPLL_FBKDIV_MASK) >> RG_HTPLL_FBKDIV;

	out_rate *= (val + 1) * 2;

	val = (readl(hdmi_phy->regs + HDMI_CON2)

	       & RG_HDMITX_TX_POSDIV_MASK);

	out_rate >>= (val >> RG_HDMITX_TX_POSDIV);



	if (readl(hdmi_phy->regs + HDMI_CON2) & RG_HDMITX_EN_TX_POSDIV)

		out_rate /= 5;



	return out_rate;

}



static const struct clk_ops mtk_hdmi_phy_pll_ops = {

	.prepare = mtk_hdmi_pll_prepare,

	.unprepare = mtk_hdmi_pll_unprepare,
@@ -174,7 +206,6 @@ static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy) 
	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);

	usleep_range(80, 100);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
@@ -186,7 +217,6 @@ static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy) 
	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);

	usleep_range(80, 100);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);

drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c

+8 −0
Original line number Diff line number Diff line
@@ -285,6 +285,14 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
	return 0;

}



static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,

					      unsigned long parent_rate)

{

	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);



	return hdmi_phy->pll_rate;

}



static const struct clk_ops mtk_hdmi_phy_pll_ops = {

	.prepare = mtk_hdmi_pll_prepare,

	.unprepare = mtk_hdmi_pll_unprepare,

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