Commit 3210e2c2 authored by Huacai Chen's avatar Huacai Chen Committed by Paolo Bonzini
Browse files

KVM: MIPS: Introduce and use cpu_guest_has_ldpte 



Loongson-3 has lddir/ldpte instructions and their related CP0 registers
are the same as HTW. So we introduce a cpu_guest_has_ldpte flag and use
it to indicate whether we need to save/restore HTW related CP0 registers
(PWBase, PWSize, PWField and PWCtl).

Acked-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
Reviewed-by: default avatarAleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
Co-developed-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <1590220602-3547-7-git-send-email-chenhc@lemote.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 8bf31295

arch/mips/include/asm/cpu-features.h

+3 −0
Original line number Diff line number Diff line
@@ -682,6 +682,9 @@ 
#ifndef cpu_guest_has_htw

#define cpu_guest_has_htw	(cpu_data[0].guest.options & MIPS_CPU_HTW)

#endif

#ifndef cpu_guest_has_ldpte

#define cpu_guest_has_ldpte	(cpu_data[0].guest.options & MIPS_CPU_LDPTE)

#endif

#ifndef cpu_guest_has_mvh

#define cpu_guest_has_mvh	(cpu_data[0].guest.options & MIPS_CPU_MVH)

#endif

arch/mips/kernel/cpu-probe.c

+3 −1
Original line number Diff line number Diff line
@@ -2017,8 +2017,10 @@ static inline void decode_cpucfg(struct cpuinfo_mips *c) 
	if (cfg2 & LOONGSON_CFG2_LEXT2)

		c->ases |= MIPS_ASE_LOONGSON_EXT2;



	if (cfg2 & LOONGSON_CFG2_LSPW)

	if (cfg2 & LOONGSON_CFG2_LSPW) {

		c->options |= MIPS_CPU_LDPTE;

		c->guest.options |= MIPS_CPU_LDPTE;

	}



	if (cfg3 & LOONGSON_CFG3_LCAMP)

		c->ases |= MIPS_ASE_LOONGSON_CAM;

arch/mips/kvm/vz.c

+13 −13
Original line number Diff line number Diff line
@@ -1706,7 +1706,7 @@ static unsigned long kvm_vz_num_regs(struct kvm_vcpu *vcpu) 
		ret += ARRAY_SIZE(kvm_vz_get_one_regs_contextconfig);

	if (cpu_guest_has_segments)

		ret += ARRAY_SIZE(kvm_vz_get_one_regs_segments);

	if (cpu_guest_has_htw)

	if (cpu_guest_has_htw || cpu_guest_has_ldpte)

		ret += ARRAY_SIZE(kvm_vz_get_one_regs_htw);

	if (cpu_guest_has_maar && !cpu_guest_has_dyn_maar)

		ret += 1 + ARRAY_SIZE(vcpu->arch.maar);
@@ -1755,7 +1755,7 @@ static int kvm_vz_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices) 
			return -EFAULT;

		indices += ARRAY_SIZE(kvm_vz_get_one_regs_segments);

	}

	if (cpu_guest_has_htw) {

	if (cpu_guest_has_htw || cpu_guest_has_ldpte) {

		if (copy_to_user(indices, kvm_vz_get_one_regs_htw,

				 sizeof(kvm_vz_get_one_regs_htw)))

			return -EFAULT;
@@ -1878,17 +1878,17 @@ static int kvm_vz_get_one_reg(struct kvm_vcpu *vcpu, 
		*v = read_gc0_segctl2();

		break;

	case KVM_REG_MIPS_CP0_PWBASE:

		if (!cpu_guest_has_htw)

		if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)

			return -EINVAL;

		*v = read_gc0_pwbase();

		break;

	case KVM_REG_MIPS_CP0_PWFIELD:

		if (!cpu_guest_has_htw)

		if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)

			return -EINVAL;

		*v = read_gc0_pwfield();

		break;

	case KVM_REG_MIPS_CP0_PWSIZE:

		if (!cpu_guest_has_htw)

		if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)

			return -EINVAL;

		*v = read_gc0_pwsize();

		break;
@@ -1896,7 +1896,7 @@ static int kvm_vz_get_one_reg(struct kvm_vcpu *vcpu, 
		*v = (long)read_gc0_wired();

		break;

	case KVM_REG_MIPS_CP0_PWCTL:

		if (!cpu_guest_has_htw)

		if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)

			return -EINVAL;

		*v = read_gc0_pwctl();

		break;
@@ -2101,17 +2101,17 @@ static int kvm_vz_set_one_reg(struct kvm_vcpu *vcpu, 
		write_gc0_segctl2(v);

		break;

	case KVM_REG_MIPS_CP0_PWBASE:

		if (!cpu_guest_has_htw)

		if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)

			return -EINVAL;

		write_gc0_pwbase(v);

		break;

	case KVM_REG_MIPS_CP0_PWFIELD:

		if (!cpu_guest_has_htw)

		if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)

			return -EINVAL;

		write_gc0_pwfield(v);

		break;

	case KVM_REG_MIPS_CP0_PWSIZE:

		if (!cpu_guest_has_htw)

		if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)

			return -EINVAL;

		write_gc0_pwsize(v);

		break;
@@ -2119,7 +2119,7 @@ static int kvm_vz_set_one_reg(struct kvm_vcpu *vcpu, 
		change_gc0_wired(MIPSR6_WIRED_WIRED, v);

		break;

	case KVM_REG_MIPS_CP0_PWCTL:

		if (!cpu_guest_has_htw)

		if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)

			return -EINVAL;

		write_gc0_pwctl(v);

		break;
@@ -2580,7 +2580,7 @@ static int kvm_vz_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 
	}



	/* restore HTW registers */

	if (cpu_guest_has_htw) {

	if (cpu_guest_has_htw || cpu_guest_has_ldpte) {

		kvm_restore_gc0_pwbase(cop0);

		kvm_restore_gc0_pwfield(cop0);

		kvm_restore_gc0_pwsize(cop0);
@@ -2685,8 +2685,8 @@ static int kvm_vz_vcpu_put(struct kvm_vcpu *vcpu, int cpu) 
	}



	/* save HTW registers if enabled in guest */

	if (cpu_guest_has_htw &&

	    kvm_read_sw_gc0_config3(cop0) & MIPS_CONF3_PW) {

	if (cpu_guest_has_ldpte || (cpu_guest_has_htw &&

	    kvm_read_sw_gc0_config3(cop0) & MIPS_CONF3_PW)) {

		kvm_save_gc0_pwbase(cop0);

		kvm_save_gc0_pwfield(cop0);

		kvm_save_gc0_pwsize(cop0);

CRA Git | Maintained and supported by SUSTech CRA and CCSE