Merge tag 'drm-for-v4.17' of git://people.freedesktop.org/~airlied/linux

Renesas R-Car LVDS Encoder

==========================

These DT bindings describe the LVDS encoder embedded in the Renesas R-Car

Gen2, R-Car Gen3 and RZ/G SoCs.

Required properties:

- compatible : Shall contain one of

  - "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders

  - "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders

  - "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders

  - "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders

  - "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders

  - "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders

  - "renesas,r8a77970-lvds" for R8A77970 (R-Car V3M) compatible LVDS encoders

  - "renesas,r8a77995-lvds" for R8A77995 (R-Car D3) compatible LVDS encoders

- reg: Base address and length for the memory-mapped registers

- clocks: A phandle + clock-specifier pair for the functional clock

- resets: A phandle + reset specifier for the module reset

Required nodes:

The LVDS encoder has two video ports. Their connections are modelled using the

OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.

- Video port 0 corresponds to the parallel RGB input

- Video port 1 corresponds to the LVDS output

Each port shall have a single endpoint.

Example:

	lvds0: lvds@feb90000 {

		compatible = "renesas,r8a7790-lvds";

		reg = <0 0xfeb90000 0 0x1c>;

		clocks = <&cpg CPG_MOD 726>;

		resets = <&cpg 726>;

		ports {

			#address-cells = <1>;

			#size-cells = <0>;

			port@0 {

				reg = <0>;

				lvds0_in: endpoint {

					remote-endpoint = <&du_out_lvds0>;

				};

			};

			port@1 {

				reg = <1>;

				lvds0_out: endpoint {

				};

			};

		};

	};

THS8135 Video DAC

-----------------

THS8134 and THS8135 Video DAC

-----------------------------

This is the binding for Texas Instruments THS8135 Video DAC bridge.

This is the binding for Texas Instruments THS8134, THS8134A, THS8134B and

THS8135 Video DAC bridges.

Required properties:

- compatible: Must be "ti,ths8135"

- compatible: Must be one of

  "ti,ths8134"

  "ti,ths8134a," "ti,ths8134"

  "ti,ths8134b", "ti,ths8134"

  "ti,ths8135"

Required nodes:

- analog: the connector has DVI analog pins

- digital: the connector has DVI digital pins

- dual-link: the connector has pins for DVI dual-link

- hpd-gpios: HPD GPIO number

Required nodes:

- Video port for DVI input

Etnaviv DRM master device

=========================

The Etnaviv DRM master device is a virtual device needed to list all

Vivante GPU cores that comprise the GPU subsystem.

Required properties:

- compatible: Should be one of

    "fsl,imx-gpu-subsystem"

    "marvell,dove-gpu-subsystem"

- cores: Should contain a list of phandles pointing to Vivante GPU devices

example:

gpu-subsystem {

	compatible = "fsl,imx-gpu-subsystem";

	cores = <&gpu_2d>, <&gpu_3d>;

};

Vivante GPU core devices

========================

- clocks: should contain one clock for entry in clock-names

  see Documentation/devicetree/bindings/clock/clock-bindings.txt

- clock-names:

   - "bus":    AXI/register clock

   - "bus":    AXI/master interface clock

   - "reg":    AHB/slave interface clock

               (only required if GPU can gate slave interface independently)

   - "core":   GPU core clock

   - "shader": Shader clock (only required if GPU has feature PIPE_3D)

- reg: Physical base address and length of the registers of controller

- reg-names: The names of register regions. The following regions are required:

  * "dsi_ctrl"

- qcom,dsi-host-index: The ID of DSI controller hardware instance. This should

  be 0 or 1, since we have 2 DSI controllers at most for now.

- interrupts: The interrupt signal from the DSI block.

- power-domains: Should be <&mmcc MDSS_GDSC>.

- clocks: Phandles to device clocks.

  * "core"

  For DSIv2, we need an additional clock:

   * "src"

  For DSI6G v2.0 onwards, we need also need the clock:

   * "byte_intf"

- assigned-clocks: Parents of "byte" and "pixel" for the given platform.

- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided

  by a DSI PHY block. See [1] for details on clock bindings.

  * "qcom,dsi-phy-28nm-lp"

  * "qcom,dsi-phy-20nm"

  * "qcom,dsi-phy-28nm-8960"

- reg: Physical base address and length of the registers of PLL, PHY and PHY

  regulator

  * "qcom,dsi-phy-14nm"

  * "qcom,dsi-phy-10nm"

- reg: Physical base address and length of the registers of PLL, PHY. Some

  revisions require the PHY regulator base address, whereas others require the

  PHY lane base address. See below for each PHY revision.

- reg-names: The names of register regions. The following regions are required:

  For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:

  * "dsi_pll"

  * "dsi_phy"

  * "dsi_phy_regulator"

  For DSI 14nm and 10nm PHYs:

  * "dsi_pll"

  * "dsi_phy"

  * "dsi_phy_lane"

- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating

  2 clocks: A byte clock (index 0), and a pixel clock (index 1).

- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should

  be 0 or 1, since we have 2 DSI PHYs at most for now.

- power-domains: Should be <&mmcc MDSS_GDSC>.

- clocks: Phandles to device clocks. See [1] for details on clock bindings.

- clock-names: the following clocks are required:

  * "iface"

  For 28nm HPM/LP, 28nm 8960 PHYs:

- vddio-supply: phandle to vdd-io regulator device node

  For 20nm PHY:

- vddio-supply: phandle to vdd-io regulator device node

- vcca-supply: phandle to vcca regulator device node

  For 14nm PHY:

- vcca-supply: phandle to vcca regulator device node

  For 10nm PHY:

- vdds-supply: phandle to vdds regulator device node

Optional properties:

- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY