Commit 31b2d7f7 authored by Russell King's avatar Russell King Committed by Linus Walleij
Browse files

gpio: omap: simplify omap_set_gpio_irqenable() 



omap_set_gpio_irqenable() calls two helpers that are almost the same
apart from whether they set or clear bits. We can consolidate these:

- in the set/clear bit register case, we can perform the operation on
  our saved context copy and write the appropriate set/clear register.
- otherwise, we can use our read-modify-write helper and invert enable
  if irqenable_inv is set.

Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
Tested-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent a47b9158

drivers/gpio/gpio-omap.c

+15 −46
Original line number Diff line number Diff line
@@ -529,57 +529,26 @@ static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) 
	return l;

}



static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)

static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,

					   unsigned offset, int enable)

{

	void __iomem *reg = bank->base;

	u32 l;

	u32 gpio_mask = BIT(offset);



	if (bank->regs->set_irqenable) {

	if (bank->regs->set_irqenable && bank->regs->clr_irqenable) {

		if (enable) {

			reg += bank->regs->set_irqenable;

		l = gpio_mask;

			bank->context.irqenable1 |= gpio_mask;

		} else {

		reg += bank->regs->irqenable;

		l = readl_relaxed(reg);

		if (bank->regs->irqenable_inv)

			l &= ~gpio_mask;

		else

			l |= gpio_mask;

		bank->context.irqenable1 = l;

	}



	writel_relaxed(l, reg);

}



static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)

{

	void __iomem *reg = bank->base;

	u32 l;



	if (bank->regs->clr_irqenable) {

			reg += bank->regs->clr_irqenable;

		l = gpio_mask;

			bank->context.irqenable1 &= ~gpio_mask;

	} else {

		reg += bank->regs->irqenable;

		l = readl_relaxed(reg);

		if (bank->regs->irqenable_inv)

			l |= gpio_mask;

		else

			l &= ~gpio_mask;

		bank->context.irqenable1 = l;

		}



	writel_relaxed(l, reg);

		writel_relaxed(gpio_mask, reg);

	} else {

		bank->context.irqenable1 =

			omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask,

				      enable ^ bank->regs->irqenable_inv);

	}



static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,

					   unsigned offset, int enable)

{

	if (enable)

		omap_enable_gpio_irqbank(bank, BIT(offset));

	else

		omap_disable_gpio_irqbank(bank, BIT(offset));

}



/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */

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