drm/atmel-hlcdc: prefer a higher rate clock as pixel-clock base (319711f9) · Commits · 戴 / test

If the divider used to get the pixel-clock is small, the granularity of the frequencies possible for the pixel-clock is quite coarse. E.g. requesting a pixel-clock of 65MHz with a sys_clk of 132MHz results in the divider being set to 3 ending up with 44MHz. By preferring the doubled sys_clk as base, the divider instead ends up as 5 yielding a pixel-clock of 52.8Mhz, which is a definite improvement. While at it, clamp the divider so that it does not overflow in case it gets big. Signed-off-by:

Peter Rosin <peda@axentia.se> Signed-off-by:

Boris Brezillon <boris.brezillon@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180824092458.13165-2-peda@axentia.se

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

+11 −7

Original line number	Diff line number	Diff line
		@@ -101,18 +101,22 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c)
		(adj->crtc_hdisplay - 1) \|
		((adj->crtc_vdisplay - 1) << 16));

		cfg = 0;
		cfg = ATMEL_HLCDC_CLKSEL;

		prate = clk_get_rate(crtc->dc->hlcdc->sys_clk);
		prate = 2 * clk_get_rate(crtc->dc->hlcdc->sys_clk);
		mode_rate = adj->crtc_clock * 1000;
		if ((prate / 2) < mode_rate) {
		prate *= 2;
		cfg \|= ATMEL_HLCDC_CLKSEL;
		}

		div = DIV_ROUND_UP(prate, mode_rate);
		if (div < 2)
		if (div < 2) {
		div = 2;
		} else if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK) {
		/* The divider ended up too big, try a lower base rate. */
		cfg &= ~ATMEL_HLCDC_CLKSEL;
		prate /= 2;
		div = DIV_ROUND_UP(prate, mode_rate);
		if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK)
		div = ATMEL_HLCDC_CLKDIV_MASK;
		}

		cfg \|= ATMEL_HLCDC_CLKDIV(div);

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