drm/amdgpu/powerper: add vega20 BACO functions (3177b3c5) · Commits · 戴 / test

drivers/gpu/drm/amd/powerplay/hwmgr/Makefile

+1 −1

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		@@ -35,7 +35,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
		vega12_thermal.o \
		pp_overdriver.o smu_helper.o \
		vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \
		vega20_thermal.o common_baco.o vega10_baco.o
		vega20_thermal.o common_baco.o vega10_baco.o vega20_baco.o

		AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))

drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c

0 → 100644

+81 −0

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		#include "amdgpu.h"
		#include "soc15.h"
		#include "soc15_hw_ip.h"
		#include "soc15_common.h"
		#include "vega20_inc.h"
		#include "vega20_ppsmc.h"
		#include "vega20_baco.h"



		static const struct soc15_baco_cmd_entry clean_baco_tbl[] =
		{
		{CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0},
		{CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_7), 0, 0, 0, 0},
		};

		int vega20_baco_get_capability(struct pp_hwmgr hwmgr, bool cap)
		{
		struct amdgpu_device adev = (struct amdgpu_device )(hwmgr->adev);
		uint32_t reg;

		*cap = false;
		if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
		return 0;

		if (((RREG32(0x17569) & 0x20000000) >> 29) == 0x1) {
		reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);

		if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
		*cap = true;
		}

		return 0;
		}

		int vega20_baco_get_state(struct pp_hwmgr hwmgr, enum BACO_STATE state)
		{
		struct amdgpu_device adev = (struct amdgpu_device )(hwmgr->adev);
		uint32_t reg;

		reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);

		if (reg & BACO_CNTL__BACO_MODE_MASK)
		/* gfx has already entered BACO state */
		*state = BACO_STATE_IN;
		else
		*state = BACO_STATE_OUT;
		return 0;
		}

		int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
		{
		struct amdgpu_device adev = (struct amdgpu_device )(hwmgr->adev);
		enum BACO_STATE cur_state;
		uint32_t data;

		vega20_baco_get_state(hwmgr, &cur_state);

		if (cur_state == state)
		/* aisc already in the target state */
		return 0;

		if (state == BACO_STATE_IN) {
		data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
		data \|= 0x80000000;
		WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);


		if(smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_EnterBaco, 0))
		return -1;

		} else if (state == BACO_STATE_OUT) {
		if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ExitBaco))
		return -1;
		if (!soc15_baco_program_registers(hwmgr, clean_baco_tbl,
		ARRAY_SIZE(clean_baco_tbl)))
		return -1;
		}

		return 0;
		}

drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h

0 → 100644

+32 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright 2018 Advanced Micro Devices, Inc.
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included in
		* all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		* OTHER DEALINGS IN THE SOFTWARE.
		*
		*/
		#ifndef __VEGA20_BOCO_H__
		#define __VEGA20_BOCO_H__
		#include "hwmgr.h"
		#include "common_baco.h"

		extern int vega20_baco_get_capability(struct pp_hwmgr hwmgr, bool cap);
		extern int vega20_baco_get_state(struct pp_hwmgr hwmgr, enum BACO_STATE state);
		extern int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);

		#endif

drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -47,6 +47,7 @@
		#include "pp_overdriver.h"
		#include "pp_thermal.h"
		#include "soc15_common.h"
		#include "vega20_baco.h"
		#include "smuio/smuio_9_0_offset.h"
		#include "smuio/smuio_9_0_sh_mask.h"
		#include "nbio/nbio_7_4_sh_mask.h"
		@@ -3591,6 +3592,10 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
		/* smu memory related */
		.notify_cac_buffer_info = vega20_notify_cac_buffer_info,
		.enable_mgpu_fan_boost = vega20_enable_mgpu_fan_boost,
		/* BACO related */
		.get_asic_baco_capability = vega20_baco_get_capability,
		.get_asic_baco_state = vega20_baco_get_state,
		.set_asic_baco_state = vega20_baco_set_state,
		};

		int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)

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