Commit 316e7f90 authored by James Morse's avatar James Morse Committed by Borislav Petkov
Browse files

x86/resctrl: Add struct rdt_cache::arch_has_{sparse, empty}_bitmaps 



Intel CPUs expect the cache bitmap provided by user-space to have on a
single span of 1s, whereas AMD can support bitmaps like 0xf00f. Arm's
MPAM support also allows sparse bitmaps.

Similarly, Intel CPUs check at least one bit set, whereas AMD CPUs are
quite happy with an empty bitmap. Arm's MPAM allows an empty bitmap.

To move resctrl out to /fs/, platform differences like this need to be
explained.

Add two resource properties arch_has_{empty,sparse}_bitmaps. Test these
around the relevant parts of cbm_validate().

Merging the validate calls causes AMD to gain the min_cbm_bits test
needed for Haswell, but as it always sets this value to 1, it will never
match.

 [ bp: Massage commit message. ]

Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Reviewed-by: default avatarBabu Moger <babu.moger@amd.com>
Reviewed-by: default avatarReinette Chatre <reinette.chatre@intel.com>
Link: https://lkml.kernel.org/r/20200708163929.2783-10-james.morse@arm.com
parent 5df3ca93

arch/x86/kernel/cpu/resctrl/core.c

+8 −6
Original line number Diff line number Diff line
@@ -922,9 +922,10 @@ static __init void rdt_init_res_defs_intel(void) 
		    r->rid == RDT_RESOURCE_L3CODE ||

		    r->rid == RDT_RESOURCE_L2 ||

		    r->rid == RDT_RESOURCE_L2DATA ||

		    r->rid == RDT_RESOURCE_L2CODE)

			r->cbm_validate = cbm_validate_intel;

		else if (r->rid == RDT_RESOURCE_MBA) {

		    r->rid == RDT_RESOURCE_L2CODE) {

			r->cache.arch_has_sparse_bitmaps = false;

			r->cache.arch_has_empty_bitmaps = false;

		} else if (r->rid == RDT_RESOURCE_MBA) {

			r->msr_base = MSR_IA32_MBA_THRTL_BASE;

			r->msr_update = mba_wrmsr_intel;

		}
@@ -941,9 +942,10 @@ static __init void rdt_init_res_defs_amd(void) 
		    r->rid == RDT_RESOURCE_L3CODE ||

		    r->rid == RDT_RESOURCE_L2 ||

		    r->rid == RDT_RESOURCE_L2DATA ||

		    r->rid == RDT_RESOURCE_L2CODE)

			r->cbm_validate = cbm_validate_amd;

		else if (r->rid == RDT_RESOURCE_MBA) {

		    r->rid == RDT_RESOURCE_L2CODE) {

			r->cache.arch_has_sparse_bitmaps = true;

			r->cache.arch_has_empty_bitmaps = true;

		} else if (r->rid == RDT_RESOURCE_MBA) {

			r->msr_base = MSR_IA32_MBA_BW_BASE;

			r->msr_update = mba_wrmsr_amd;

		}

arch/x86/kernel/cpu/resctrl/ctrlmondata.c

+10 −29
Original line number Diff line number Diff line
@@ -76,12 +76,14 @@ int parse_bw(struct rdt_parse_data *data, struct rdt_resource *r, 
}



/*

 * Check whether a cache bit mask is valid. The SDM says:

 * Check whether a cache bit mask is valid.

 * For Intel the SDM says:

 *	Please note that all (and only) contiguous '1' combinations

 *	are allowed (e.g. FFFFH, 0FF0H, 003CH, etc.).

 * Additionally Haswell requires at least two bits set.

 * AMD allows non-contiguous bitmasks.

 */

bool cbm_validate_intel(char *buf, u32 *data, struct rdt_resource *r)

static bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r)

{

	unsigned long first_bit, zero_bit, val;

	unsigned int cbm_len = r->cache.cbm_len;
@@ -93,7 +95,8 @@ bool cbm_validate_intel(char *buf, u32 *data, struct rdt_resource *r) 
		return false;

	}



	if (val == 0 || val > r->default_ctrl) {

	if ((!r->cache.arch_has_empty_bitmaps && val == 0) ||

	    val > r->default_ctrl) {

		rdt_last_cmd_puts("Mask out of range\n");

		return false;

	}
@@ -101,7 +104,9 @@ bool cbm_validate_intel(char *buf, u32 *data, struct rdt_resource *r) 
	first_bit = find_first_bit(&val, cbm_len);

	zero_bit = find_next_zero_bit(&val, cbm_len, first_bit);



	if (find_next_bit(&val, cbm_len, zero_bit) < cbm_len) {

	/* Are non-contiguous bitmaps allowed? */

	if (!r->cache.arch_has_sparse_bitmaps &&

	    (find_next_bit(&val, cbm_len, zero_bit) < cbm_len)) {

		rdt_last_cmd_printf("The mask %lx has non-consecutive 1-bits\n", val);

		return false;

	}
@@ -116,30 +121,6 @@ bool cbm_validate_intel(char *buf, u32 *data, struct rdt_resource *r) 
	return true;

}



/*

 * Check whether a cache bit mask is valid. AMD allows non-contiguous

 * bitmasks

 */

bool cbm_validate_amd(char *buf, u32 *data, struct rdt_resource *r)

{

	unsigned long val;

	int ret;



	ret = kstrtoul(buf, 16, &val);

	if (ret) {

		rdt_last_cmd_printf("Non-hex character in the mask %s\n", buf);

		return false;

	}



	if (val > r->default_ctrl) {

		rdt_last_cmd_puts("Mask out of range\n");

		return false;

	}



	*data = val;

	return true;

}



/*

 * Read one cache bit mask (hex). Check that it is valid for the current

 * resource type.
@@ -165,7 +146,7 @@ int parse_cbm(struct rdt_parse_data *data, struct rdt_resource *r, 
		return -EINVAL;

	}



	if (!r->cbm_validate(data->buf, &cbm_val, r))

	if (!cbm_validate(data->buf, &cbm_val, r))

		return -EINVAL;



	if ((rdtgrp->mode == RDT_MODE_EXCLUSIVE ||

arch/x86/kernel/cpu/resctrl/internal.h

+4 −4
Original line number Diff line number Diff line
@@ -358,6 +358,8 @@ struct msr_param { 
 *			in a cache bit mask

 * @shareable_bits:	Bitmask of shareable resource with other

 *			executing entities

 * @arch_has_sparse_bitmaps:	True if a bitmap like f00f is valid.

 * @arch_has_empty_bitmaps:	True if the '0' bitmap is valid.

 */

struct rdt_cache {

	unsigned int	cbm_len;
@@ -365,6 +367,8 @@ struct rdt_cache { 
	unsigned int	cbm_idx_mult;

	unsigned int	cbm_idx_offset;

	unsigned int	shareable_bits;

	bool		arch_has_sparse_bitmaps;

	bool		arch_has_empty_bitmaps;

};



/**
@@ -434,7 +438,6 @@ struct rdt_parse_data { 
 * @cache:		Cache allocation related data

 * @format_str:		Per resource format string to show domain value

 * @parse_ctrlval:	Per resource function pointer to parse control values

 * @cbm_validate	Cache bitmask validate function

 * @evt_list:		List of monitoring events

 * @num_rmid:		Number of RMIDs available

 * @mon_scale:		cqm counter * mon_scale = occupancy in bytes
@@ -461,7 +464,6 @@ struct rdt_resource { 
	int (*parse_ctrlval)(struct rdt_parse_data *data,

			     struct rdt_resource *r,

			     struct rdt_domain *d);

	bool (*cbm_validate)(char *buf, u32 *data, struct rdt_resource *r);

	struct list_head	evt_list;

	int			num_rmid;

	unsigned int		mon_scale;
@@ -604,8 +606,6 @@ void cqm_setup_limbo_handler(struct rdt_domain *dom, unsigned long delay_ms); 
void cqm_handle_limbo(struct work_struct *work);

bool has_busy_rmid(struct rdt_resource *r, struct rdt_domain *d);

void __check_limbo(struct rdt_domain *d, bool force_free);

bool cbm_validate_intel(char *buf, u32 *data, struct rdt_resource *r);

bool cbm_validate_amd(char *buf, u32 *data, struct rdt_resource *r);

void rdt_domain_reconfigure_cdp(struct rdt_resource *r);



#endif /* _ASM_X86_RESCTRL_INTERNAL_H */

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