Commit 3144bedf authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-v5.1-samsung' of... 

Merge tag 'clk-v5.1-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung

Pull Samsung clk driver updates from Sylwester Nawrocki:

Exynos5433 clock driver update adding support for selected clocks
of the IMEM CMU required for the cryptographic subsystem (SlimSS).

* tag 'clk-v5.1-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
  clk: samsung: exynos5433: Add selected IMEM clocks
  clk: samsung: dt-bindings: Document Exynos5433 IMEM CMU
  clk: samsung: exynos5433: Fix name typo in sssx
  clk: samsung: exynos5433: Fix definition of CLK_ACLK_IMEM_{200, 266} clocks
  clk: samsung: dt-bindings: Add Exynos5433 IMEM CMU clock IDs
parents bfeffd15 81faa30d

Documentation/devicetree/bindings/clock/exynos5433-clock.txt

+23 −0
Original line number Diff line number Diff line
@@ -50,6 +50,8 @@ Required Properties: 
    IPs.

  - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1

    which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.

  - "samsung,exynos5433-cmu-imem"   - clock controller compatible for CMU_IMEM

    which generates clocks for SSS (Security SubSystem) and SlimSSS IPs.



- reg: physical base address of the controller and length of memory mapped

  region.
@@ -168,6 +170,12 @@ Required Properties: 
		- aclk_cam1_400

		- aclk_cam1_552



	Input clocks for imem clock controller:

		- oscclk

		- aclk_imem_sssx_266

		- aclk_imem_266

		- aclk_imem_200



Optional properties:

  - power-domains: a phandle to respective power domain node as described by

	generic PM domain bindings (see power/power_domain.txt for more
@@ -469,6 +477,21 @@ Example 2: Examples of clock controller nodes are listed below. 
		power-domains = <&pd_cam1>;

	};



	cmu_imem: clock-controller@11060000 {

		compatible = "samsung,exynos5433-cmu-imem";

		reg = <0x11060000 0x1000>;

		#clock-cells = <1>;



		clock-names = "oscclk",

			"aclk_imem_sssx_266",

			"aclk_imem_266",

			"aclk_imem_200";

		clocks = <&xxti>,

			<&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,

			<&cmu_top CLK_DIV_ACLK_IMEM_266>,

			<&cmu_top CLK_DIV_ACLK_IMEM_200>;

	};



Example 3: UART controller node that consumes the clock generated by the clock

	   controller.

drivers/clk/samsung/clk-exynos5433.c

+35 −3
Original line number Diff line number Diff line
@@ -559,7 +559,7 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = { 
	/* ENABLE_ACLK_TOP */

	GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",

			ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0),

	GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",

	GATE(CLK_ACLK_IMEM_SSSX_266, "aclk_imem_sssx_266",

			"div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,

			29, CLK_IGNORE_UNUSED, 0),

	GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
@@ -568,10 +568,10 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = { 
	GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",

			ENABLE_ACLK_TOP, 25,

			CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),

	GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",

	GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_200",

			ENABLE_ACLK_TOP, 24,

			CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),

	GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",

	GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_266",

			ENABLE_ACLK_TOP, 23,

			CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),

	GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
@@ -5467,6 +5467,35 @@ static const struct samsung_cmu_info cam1_cmu_info __initconst = { 
	.clk_name		= "aclk_cam1_400",

};



/*

 * Register offset definitions for CMU_IMEM

 */

#define ENABLE_ACLK_IMEM_SLIMSSS		0x080c

#define ENABLE_PCLK_IMEM_SLIMSSS		0x0908



static const unsigned long imem_clk_regs[] __initconst = {

	ENABLE_ACLK_IMEM_SLIMSSS,

	ENABLE_PCLK_IMEM_SLIMSSS,

};



static const struct samsung_gate_clock imem_gate_clks[] __initconst = {

	/* ENABLE_ACLK_IMEM_SLIMSSS */

	GATE(CLK_ACLK_SLIMSSS, "aclk_slimsss", "aclk_imem_sssx_266",

			ENABLE_ACLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),



	/* ENABLE_PCLK_IMEM_SLIMSSS */

	GATE(CLK_PCLK_SLIMSSS, "pclk_slimsss", "aclk_imem_200",

			ENABLE_PCLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),

};



static const struct samsung_cmu_info imem_cmu_info __initconst = {

	.gate_clks		= imem_gate_clks,

	.nr_gate_clks		= ARRAY_SIZE(imem_gate_clks),

	.nr_clk_ids		= IMEM_NR_CLK,

	.clk_regs		= imem_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(imem_clk_regs),

	.clk_name		= "aclk_imem_200",

};



struct exynos5433_cmu_data {

	struct samsung_clk_reg_dump *clk_save;
@@ -5654,6 +5683,9 @@ static const struct of_device_id exynos5433_cmu_of_match[] = { 
	}, {

		.compatible = "samsung,exynos5433-cmu-mscl",

		.data = &mscl_cmu_info,

	}, {

		.compatible = "samsung,exynos5433-cmu-imem",

		.data = &imem_cmu_info,

	}, {

	},

};

include/dt-bindings/clock/exynos5433.h

+7 −1
Original line number Diff line number Diff line
@@ -156,7 +156,7 @@ 
#define CLK_ACLK_G2D_266		220

#define CLK_ACLK_G2D_400		221

#define CLK_ACLK_G3D_400		222

#define CLK_ACLK_IMEM_SSX_266		223

#define CLK_ACLK_IMEM_SSSX_266		223

#define CLK_ACLK_BUS0_400		224

#define CLK_ACLK_BUS1_400		225

#define CLK_ACLK_IMEM_200		226
@@ -1406,4 +1406,10 @@ 


#define CAM1_NR_CLK					113



/* CMU_IMEM */

#define CLK_ACLK_SLIMSSS		2

#define CLK_PCLK_SLIMSSS		35



#define IMEM_NR_CLK			36



#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */

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