ARM: dts: r8a7743: Add CMT SoC specific support

						  IRQ_TYPE_LEVEL_LOW)>;

		};

		cmt0: timer@ffca0000 {

			compatible = "renesas,r8a7743-cmt0",

				     "renesas,rcar-gen2-cmt0";

			reg = <0 0xffca0000 0 0x1004>;

			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 124>;

			clock-names = "fck";

			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;

			resets = <&cpg 124>;

			status = "disabled";

		};

		cmt1: timer@e6130000 {

			compatible = "renesas,r8a7743-cmt1",

				     "renesas,rcar-gen2-cmt1";

			reg = <0 0xe6130000 0 0x1004>;

			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 329>;

			clock-names = "fck";

			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;

			resets = <&cpg 329>;

			status = "disabled";

		};

		cpg: clock-controller@e6150000 {

			compatible = "renesas,r8a7743-cpg-mssr";

			reg = <0 0xe6150000 0 0x1000>;