Commit 30d6c72c authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge remote branch 'anholt/drm-intel-next' into drm-next-stage 

* anholt/drm-intel-next:
  drm/i915: Record batch buffer following GPU error
  drm/i915: give up on 8xx lid status
  drm/i915: reduce some of the duplication of tiling checking
  drm/i915: blow away userspace mappings before fence change
  drm/i915: move a gtt flush to the correct place
  agp/intel: official names for Pineview and Ironlake
  drm/i915: overlay: drop superflous gpu flushes
  drm/i915: overlay: nuke readback to flush wc caches
  drm/i915: provide self-refresh status in debugfs
  drm/i915: provide FBC status in debugfs
  drm/i915: fix drps disable so unload & re-load works
  drm/i915: Fix OGLC performance regression on 945
  drm/i915: Deobfuscate the render p-state obfuscation
  drm/i915: add dynamic performance control support for Ironlake
  drm/i915: enable memory self refresh on 9xx
  drm/i915: Don't reserve compatibility fence regs in KMS mode.
  drm/i915: Keep MCHBAR always enabled
  drm/i915: Replace open-coded eviction in i915_gem_idle()
parents de19322d 9df30794

drivers/char/agp/intel-agp.c

+6 −6
Original line number Diff line number Diff line
@@ -2345,9 +2345,9 @@ static const struct intel_driver_description { 
		NULL, &intel_g33_driver },

	{ PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",

		NULL, &intel_g33_driver },

	{ PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, 0, "Pineview",

	{ PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, 0, "GMA3150",

		NULL, &intel_g33_driver },

	{ PCI_DEVICE_ID_INTEL_PINEVIEW_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_IG, 0, "Pineview",

	{ PCI_DEVICE_ID_INTEL_PINEVIEW_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_IG, 0, "GMA3150",

		NULL, &intel_g33_driver },

	{ PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,

	    "GM45", NULL, &intel_i965_driver },
@@ -2362,13 +2362,13 @@ static const struct intel_driver_description { 
	{ PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,

	    "G41", NULL, &intel_i965_driver },

	{ PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 0,

	    "Ironlake/D", NULL, &intel_i965_driver },

	    "HD Graphics", NULL, &intel_i965_driver },

	{ PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,

	    "Ironlake/M", NULL, &intel_i965_driver },

	    "HD Graphics", NULL, &intel_i965_driver },

	{ PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,

	    "Ironlake/MA", NULL, &intel_i965_driver },

	    "HD Graphics", NULL, &intel_i965_driver },

	{ PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,

	    "Ironlake/MC2", NULL, &intel_i965_driver },

	    "HD Graphics", NULL, &intel_i965_driver },

	{ 0, 0, 0, NULL, NULL, NULL }

};

drivers/gpu/drm/i915/i915_debugfs.c

+251 −0
Original line number Diff line number Diff line
@@ -350,6 +350,36 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data) 
	return 0;

}



static const char *pin_flag(int pinned)

{

	if (pinned > 0)

		return " P";

	else if (pinned < 0)

		return " p";

	else

		return "";

}



static const char *tiling_flag(int tiling)

{

	switch (tiling) {

	default:

	case I915_TILING_NONE: return "";

	case I915_TILING_X: return " X";

	case I915_TILING_Y: return " Y";

	}

}



static const char *dirty_flag(int dirty)

{

	return dirty ? " dirty" : "";

}



static const char *purgeable_flag(int purgeable)

{

	return purgeable ? " purgeable" : "";

}



static int i915_error_state(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;
@@ -357,6 +387,7 @@ static int i915_error_state(struct seq_file *m, void *unused) 
	drm_i915_private_t *dev_priv = dev->dev_private;

	struct drm_i915_error_state *error;

	unsigned long flags;

	int i, page, offset, elt;



	spin_lock_irqsave(&dev_priv->error_lock, flags);

	if (!dev_priv->first_error) {
@@ -368,6 +399,7 @@ static int i915_error_state(struct seq_file *m, void *unused) 


	seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,

		   error->time.tv_usec);

	seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);

	seq_printf(m, "EIR: 0x%08x\n", error->eir);

	seq_printf(m, "  PGTBL_ER: 0x%08x\n", error->pgtbl_er);

	seq_printf(m, "  INSTPM: 0x%08x\n", error->instpm);
@@ -379,6 +411,59 @@ static int i915_error_state(struct seq_file *m, void *unused) 
		seq_printf(m, "  INSTPS: 0x%08x\n", error->instps);

		seq_printf(m, "  INSTDONE1: 0x%08x\n", error->instdone1);

	}

	seq_printf(m, "seqno: 0x%08x\n", error->seqno);



	if (error->active_bo_count) {

		seq_printf(m, "Buffers [%d]:\n", error->active_bo_count);



		for (i = 0; i < error->active_bo_count; i++) {

			seq_printf(m, "  %08x %8zd %08x %08x %08x%s%s%s%s",

				   error->active_bo[i].gtt_offset,

				   error->active_bo[i].size,

				   error->active_bo[i].read_domains,

				   error->active_bo[i].write_domain,

				   error->active_bo[i].seqno,

				   pin_flag(error->active_bo[i].pinned),

				   tiling_flag(error->active_bo[i].tiling),

				   dirty_flag(error->active_bo[i].dirty),

				   purgeable_flag(error->active_bo[i].purgeable));



			if (error->active_bo[i].name)

				seq_printf(m, " (name: %d)", error->active_bo[i].name);

			if (error->active_bo[i].fence_reg != I915_FENCE_REG_NONE)

				seq_printf(m, " (fence: %d)", error->active_bo[i].fence_reg);



			seq_printf(m, "\n");

		}

	}



	for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) {

		if (error->batchbuffer[i]) {

			struct drm_i915_error_object *obj = error->batchbuffer[i];



			seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset);

			offset = 0;

			for (page = 0; page < obj->page_count; page++) {

				for (elt = 0; elt < PAGE_SIZE/4; elt++) {

					seq_printf(m, "%08x :  %08x\n", offset, obj->pages[page][elt]);

					offset += 4;

				}

			}

		}

	}



	if (error->ringbuffer) {

		struct drm_i915_error_object *obj = error->ringbuffer;



		seq_printf(m, "--- ringbuffer = 0x%08x\n", obj->gtt_offset);

		offset = 0;

		for (page = 0; page < obj->page_count; page++) {

			for (elt = 0; elt < PAGE_SIZE/4; elt++) {

				seq_printf(m, "%08x :  %08x\n", offset, obj->pages[page][elt]);

				offset += 4;

			}

		}

	}



out:

	spin_unlock_irqrestore(&dev_priv->error_lock, flags);
@@ -386,6 +471,165 @@ out: 
	return 0;

}



static int i915_rstdby_delays(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	u16 crstanddelay = I915_READ16(CRSTANDVID);



	seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));



	return 0;

}



static int i915_cur_delayinfo(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	u16 rgvswctl = I915_READ16(MEMSWCTL);



	seq_printf(m, "Last command: 0x%01x\n", (rgvswctl >> 13) & 0x3);

	seq_printf(m, "Command status: %d\n", (rgvswctl >> 12) & 1);

	seq_printf(m, "P%d DELAY 0x%02x\n", (rgvswctl >> 8) & 0xf,

		   rgvswctl & 0x3f);



	return 0;

}



static int i915_delayfreq_table(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	u32 delayfreq;

	int i;



	for (i = 0; i < 16; i++) {

		delayfreq = I915_READ(PXVFREQ_BASE + i * 4);

		seq_printf(m, "P%02dVIDFREQ: 0x%08x\n", i, delayfreq);

	}



	return 0;

}



static inline int MAP_TO_MV(int map)

{

	return 1250 - (map * 25);

}



static int i915_inttoext_table(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	u32 inttoext;

	int i;



	for (i = 1; i <= 32; i++) {

		inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);

		seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);

	}



	return 0;

}



static int i915_drpc_info(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	u32 rgvmodectl = I915_READ(MEMMODECTL);



	seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?

		   "yes" : "no");

	seq_printf(m, "Boost freq: %d\n",

		   (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>

		   MEMMODE_BOOST_FREQ_SHIFT);

	seq_printf(m, "HW control enabled: %s\n",

		   rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");

	seq_printf(m, "SW control enabled: %s\n",

		   rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");

	seq_printf(m, "Gated voltage change: %s\n",

		   rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");

	seq_printf(m, "Starting frequency: P%d\n",

		   (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);

	seq_printf(m, "Max frequency: P%d\n",

		   (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);

	seq_printf(m, "Min frequency: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));



	return 0;

}



static int i915_fbc_status(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	struct drm_crtc *crtc;

	drm_i915_private_t *dev_priv = dev->dev_private;

	bool fbc_enabled = false;



	if (!dev_priv->display.fbc_enabled) {

		seq_printf(m, "FBC unsupported on this chipset\n");

		return 0;

	}



	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

		if (!crtc->enabled)

			continue;

		if (dev_priv->display.fbc_enabled(crtc))

			fbc_enabled = true;

	}



	if (fbc_enabled) {

		seq_printf(m, "FBC enabled\n");

	} else {

		seq_printf(m, "FBC disabled: ");

		switch (dev_priv->no_fbc_reason) {

		case FBC_STOLEN_TOO_SMALL:

			seq_printf(m, "not enough stolen memory");

			break;

		case FBC_UNSUPPORTED_MODE:

			seq_printf(m, "mode not supported");

			break;

		case FBC_MODE_TOO_LARGE:

			seq_printf(m, "mode too large");

			break;

		case FBC_BAD_PLANE:

			seq_printf(m, "FBC unsupported on plane");

			break;

		case FBC_NOT_TILED:

			seq_printf(m, "scanout buffer not tiled");

			break;

		default:

			seq_printf(m, "unknown reason");

		}

		seq_printf(m, "\n");

	}

	return 0;

}



static int i915_sr_status(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	bool sr_enabled = false;



	if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev))

		sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;

	else if (IS_I915GM(dev))

		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;

	else if (IS_PINEVIEW(dev))

		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;



	seq_printf(m, "self-refresh: %s\n", sr_enabled ? "enabled" :

		   "disabled");



	return 0;

}



static int

i915_wedged_open(struct inode *inode,

		 struct file *filp)
@@ -503,6 +747,13 @@ static struct drm_info_list i915_debugfs_list[] = { 
	{"i915_ringbuffer_info", i915_ringbuffer_info, 0},

	{"i915_batchbuffers", i915_batchbuffer_info, 0},

	{"i915_error_state", i915_error_state, 0},

	{"i915_rstdby_delays", i915_rstdby_delays, 0},

	{"i915_cur_delayinfo", i915_cur_delayinfo, 0},

	{"i915_delayfreq_table", i915_delayfreq_table, 0},

	{"i915_inttoext_table", i915_inttoext_table, 0},

	{"i915_drpc_info", i915_drpc_info, 0},

	{"i915_fbc_status", i915_fbc_status, 0},

	{"i915_sr_status", i915_sr_status, 0},

};

#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)

drivers/gpu/drm/i915/i915_dma.c

+125 −0
Original line number Diff line number Diff line
@@ -35,6 +35,8 @@ 
#include "i915_drv.h"

#include "i915_trace.h"

#include <linux/vgaarb.h>

#include <linux/acpi.h>

#include <linux/pnp.h>



/* Really want an OS-independent resettable timer.  Would like to have

 * this loop run for (eg) 3 sec, but have the timer reset every time
@@ -933,6 +935,120 @@ static int i915_get_bridge_dev(struct drm_device *dev) 
	return 0;

}



#define MCHBAR_I915 0x44

#define MCHBAR_I965 0x48

#define MCHBAR_SIZE (4*4096)



#define DEVEN_REG 0x54

#define   DEVEN_MCHBAR_EN (1 << 28)



/* Allocate space for the MCH regs if needed, return nonzero on error */

static int

intel_alloc_mchbar_resource(struct drm_device *dev)

{

	drm_i915_private_t *dev_priv = dev->dev_private;

	int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;

	u32 temp_lo, temp_hi = 0;

	u64 mchbar_addr;

	int ret = 0;



	if (IS_I965G(dev))

		pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);

	pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);

	mchbar_addr = ((u64)temp_hi << 32) | temp_lo;



	/* If ACPI doesn't have it, assume we need to allocate it ourselves */

#ifdef CONFIG_PNP

	if (mchbar_addr &&

	    pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {

		ret = 0;

		goto out;

	}

#endif



	/* Get some space for it */

	ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,

				     MCHBAR_SIZE, MCHBAR_SIZE,

				     PCIBIOS_MIN_MEM,

				     0,   pcibios_align_resource,

				     dev_priv->bridge_dev);

	if (ret) {

		DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);

		dev_priv->mch_res.start = 0;

		goto out;

	}



	if (IS_I965G(dev))

		pci_write_config_dword(dev_priv->bridge_dev, reg + 4,

				       upper_32_bits(dev_priv->mch_res.start));



	pci_write_config_dword(dev_priv->bridge_dev, reg,

			       lower_32_bits(dev_priv->mch_res.start));

out:

	return ret;

}



/* Setup MCHBAR if possible, return true if we should disable it again */

static void

intel_setup_mchbar(struct drm_device *dev)

{

	drm_i915_private_t *dev_priv = dev->dev_private;

	int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;

	u32 temp;

	bool enabled;



	dev_priv->mchbar_need_disable = false;



	if (IS_I915G(dev) || IS_I915GM(dev)) {

		pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);

		enabled = !!(temp & DEVEN_MCHBAR_EN);

	} else {

		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);

		enabled = temp & 1;

	}



	/* If it's already enabled, don't have to do anything */

	if (enabled)

		return;



	if (intel_alloc_mchbar_resource(dev))

		return;



	dev_priv->mchbar_need_disable = true;



	/* Space is allocated or reserved, so enable it. */

	if (IS_I915G(dev) || IS_I915GM(dev)) {

		pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,

				       temp | DEVEN_MCHBAR_EN);

	} else {

		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);

		pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);

	}

}



static void

intel_teardown_mchbar(struct drm_device *dev)

{

	drm_i915_private_t *dev_priv = dev->dev_private;

	int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;

	u32 temp;



	if (dev_priv->mchbar_need_disable) {

		if (IS_I915G(dev) || IS_I915GM(dev)) {

			pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);

			temp &= ~DEVEN_MCHBAR_EN;

			pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);

		} else {

			pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);

			temp &= ~1;

			pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);

		}

	}



	if (dev_priv->mch_res.start)

		release_resource(&dev_priv->mch_res);

}



/**

 * i915_probe_agp - get AGP bootup configuration

 * @pdev: PCI device
@@ -1133,6 +1249,7 @@ static void i915_setup_compression(struct drm_device *dev, int size) 
	/* Leave 1M for line length buffer & misc. */

	compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);

	if (!compressed_fb) {

		dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;

		i915_warn_stolen(dev);

		return;

	}
@@ -1140,6 +1257,7 @@ static void i915_setup_compression(struct drm_device *dev, int size) 
	compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);

	if (!compressed_fb) {

		i915_warn_stolen(dev);

		dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;

		return;

	}
@@ -1450,6 +1568,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
		dev->driver->get_vblank_counter = gm45_get_vblank_counter;

	}



	/* Try to make sure MCHBAR is enabled before poking at it */

	intel_setup_mchbar(dev);



	i915_gem_load(dev);



	/* Init HWS */
@@ -1523,6 +1644,8 @@ int i915_driver_unload(struct drm_device *dev) 
{

	struct drm_i915_private *dev_priv = dev->dev_private;



	i915_destroy_error_state(dev);



	destroy_workqueue(dev_priv->wq);

	del_timer_sync(&dev_priv->hangcheck_timer);
@@ -1569,6 +1692,8 @@ int i915_driver_unload(struct drm_device *dev) 
		intel_cleanup_overlay(dev);

	}



	intel_teardown_mchbar(dev);



	pci_dev_put(dev_priv->bridge_dev);

	kfree(dev->dev_private);

drivers/gpu/drm/i915/i915_drv.c

+5 −0
Original line number Diff line number Diff line
@@ -571,6 +571,11 @@ static int __init i915_init(void) 
		driver.driver_features &= ~DRIVER_MODESET;

#endif



	if (!(driver.driver_features & DRIVER_MODESET)) {

		driver.suspend = i915_suspend;

		driver.resume = i915_resume;

	}



	return drm_init(&driver);

}

drivers/gpu/drm/i915/i915_drv.h

+40 −1
Original line number Diff line number Diff line
@@ -150,7 +150,27 @@ struct drm_i915_error_state { 
	u32 instps;

	u32 instdone1;

	u32 seqno;

	u64 bbaddr;

	struct timeval time;

	struct drm_i915_error_object {

		int page_count;

		u32 gtt_offset;

		u32 *pages[0];

	} *ringbuffer, *batchbuffer[2];

	struct drm_i915_error_buffer {

		size_t size;

		u32 name;

		u32 seqno;

		u32 gtt_offset;

		u32 read_domains;

		u32 write_domain;

		u32 fence_reg;

		s32 pinned:2;

		u32 tiling:2;

		u32 dirty:1;

		u32 purgeable:1;

	} *active_bo;

	u32 active_bo_count;

};



struct drm_i915_display_funcs {
@@ -192,6 +212,14 @@ struct intel_device_info { 
	u8 cursor_needs_physical : 1;

};



enum no_fbc_reason {

	FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */

	FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */

	FBC_MODE_TOO_LARGE, /* mode too large for compression */

	FBC_BAD_PLANE, /* fbc not supported on plane */

	FBC_NOT_TILED, /* buffer not tiled */

};



typedef struct drm_i915_private {

	struct drm_device *dev;
@@ -452,6 +480,7 @@ typedef struct drm_i915_private { 
	u32 savePIPEB_DATA_N1;

	u32 savePIPEB_LINK_M1;

	u32 savePIPEB_LINK_N1;

	u32 saveMCHBAR_RENDER_STANDBY;



	struct {

		struct drm_mm gtt_space;
@@ -590,6 +619,14 @@ typedef struct drm_i915_private { 
	int child_dev_num;

	struct child_device_config *child_dev;

	struct drm_connector *int_lvds_connector;



	bool mchbar_need_disable;



	u8 cur_delay;

	u8 min_delay;

	u8 max_delay;



	enum no_fbc_reason no_fbc_reason;

} drm_i915_private_t;



/** driver private structure attached to each drm_gem_object */
@@ -761,6 +798,7 @@ extern int i965_reset(struct drm_device *dev, u8 flags); 


/* i915_irq.c */

void i915_hangcheck_elapsed(unsigned long data);

void i915_destroy_error_state(struct drm_device *dev);

extern int i915_irq_emit(struct drm_device *dev, void *data,

			 struct drm_file *file_priv);

extern int i915_irq_wait(struct drm_device *dev, void *data,
@@ -897,7 +935,8 @@ void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj); 
void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);

bool i915_tiling_ok(struct drm_device *dev, int stride, int size,

		    int tiling_mode);

bool i915_obj_fenceable(struct drm_device *dev, struct drm_gem_object *obj);

bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj,

				     int tiling_mode);



/* i915_gem_debug.c */

void i915_gem_dump_object(struct drm_gem_object *obj, int len,

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